MCF5281CVM66J Freescale Semiconductor, MCF5281CVM66J Datasheet - Page 397
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MCF5281CVM66J
Manufacturer Part Number
MCF5281CVM66J
Description
IC MPU 256K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5281CVM66J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
150
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF528x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5282-KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5281CVM66J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
- Current page: 397 of 766
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21.2.2
The DTXMRn registers program DMA request and increment modes for the timers.
21.2.3
DTERn, shown in
DTERn[REF]. This reporting happens regardless of the corresponding DMA request or interrupt enable
values, DTXMRn[DMAEN] and DTMRn[ORRI,CE].
Writing a 1 to DTERn[REF] or DTERn[CAP] clears it (writing a 0 does not affect bit value); both bits can
be cleared at the same time. If configured to generate an interrupt request, clear REF and CAP early in the
interrupt service routine so the timer module can negate the interrupt request signal to the interrupt
controller. If configured to generate a DMA request, processing of the DMA data transfer automatically
clears the REF and CAP flags via the internal DMA ACK signal.
Freescale Semiconductor
MODE16
DMAEN
Field
6–1
7
0
IPSBAR
Offset:
Reset:
DMA request. Enables DMA request output on counter reference match or capture edge event.
0 DMA request disabled
1 DMA request enabled
Reserved, must be cleared.
Selects the increment mode for the timer. Setting MODE16 is intended to exercise the upper bits of the 32-bit timer
in diagnostic software without requiring the timer to count through its entire dynamic range. When set, the counter’s
upper 16 bits mirror its lower 16 bits. All 32 bits of the counter remain compared to the reference value.
0 Increment timer by 1
1 Increment timer by 65,537
W
R
DMA Timer Extended Mode Registers (DTXMRn)
DMA Timer Event Registers (DTERn)
0x00_0402 (DTXMR0)
0x00_0442 (DTXMR1)
0x00_0482 (DTXMR2)
0x00_04C2 (DTXMR3)
DMAEN
0
7
Figure
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
21-4, reports capture or reference events by setting DTERn[CAP] or
6
0
0
Table 21-3. DTXMRn Field Descriptions
Figure 21-3. DTXMRn Registers
0
0
5
0
0
4
Description
0
0
3
0
0
2
Access: User read/write
DMA Timers (DTIM0–DTIM3)
0
0
1
MODE16
0
0
21-5
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