MCF5281CVM66J Freescale Semiconductor, MCF5281CVM66J Datasheet - Page 591
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MCF5281CVM66J
Manufacturer Part Number
MCF5281CVM66J
Description
IC MPU 256K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5281CVM66J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
150
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF528x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5282-KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5281CVM66J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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These conditions will cause a pulsed reset of the periodic/interval timer during use:
During stop mode, the periodic/interval timer is held in reset. Because stop mode causes QACR1 and
QACR2 to be reset to 0, a valid periodic or interval timer mode must be written after leaving stop mode to
release the timer from reset.
When QADC debug mode is entered and a periodic or interval timer mode is selected, the timer counter
is reset after the conversion in progress completes. When the periodic or interval timer mode has been
enabled (the timer is counting), but a trigger event has not been issued, debug mode takes effect
immediately, and the timer is held in reset. Removal of the QADC debug condition restarts the counter
from the beginning. Refer to
28.8.10 Conversion Command Word Table
The conversion command word (CCW) table is 64 half-word (128 byte) long RAM with 10 bits of each
entry implemented. The CCW table is written by the user and is not modified by the QADC. Each CCW
requests the conversion of one analog channel to a digital result. The CCW specifies the analog channel
number, the input sample time, and whether the queue is to pause after the current CCW. The 10
implemented bits of the CCW can be read and written. The remaining six bits are unimplemented and read
as 0s; write operations have no effect. Each location in the CCW table corresponds to a location in the
result word table. When a conversion is completed for a CCW entry, the 10-bit result is written in the
corresponding result word entry.
The beginning of queue 1 is the first location in the CCW table. The first location of queue 2 is specified
by the beginning of queue 2 pointer field (BQ2) in QACR2. To dedicate the entire CCW table to queue 1,
place queue 2 in disabled mode and write BQ2 to 64 or greater. To dedicate the entire CCW table to queue
2, place queue 1 in disabled mode and set BQ2 to the first location in the CCW table (CCW0).
Figure 28-43
Freescale Semiconductor
•
•
•
•
•
•
•
Both queue 1 and queue 2 are programmed to any mode which does not use the periodic/interval
timer.
System reset is asserted.
Stop mode is enabled.
Debug mode is enabled.
A queue 1 operating mode change to a mode which uses the periodic/interval timer, even if queue
2 is already using the timer
A queue 2 operating mode change to a mode which uses the periodic/interval timer, provided queue
1 is not in a mode which uses the periodic/interval timer
Roll over of the timer
illustrates the operation of the queue structure.
Interval timer single-scan mode does not start the periodic/interval timer
until the single-scan enable bit is set.
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Section 28.3.1, “Debug Mode
NOTE
for more information.
Queued Analog-to-Digital Converter (QADC)
28-53
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