MCF5281CVM66J Freescale Semiconductor, MCF5281CVM66J Datasheet - Page 289
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MCF5281CVM66J
Manufacturer Part Number
MCF5281CVM66J
Description
IC MPU 256K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5281CVM66J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
150
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF528x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5282-KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5281CVM66J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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15.2.4
Synchronous DRAMs have a prescribed initialization sequence. The DRAM controller supports this
sequence with the following procedure:
Freescale Semiconductor
SDRAM_CS[0] or [1]
(DCR[COC] = 0)
1. SDRAM control signals are reset to idle state. Wait the prescribed period after reset before any
2. Initialize the DCR, DACR, and DMR in their operational configuration. Do not yet enable
3. Issue a
4. Enable refresh (set DACR[RE]) and wait for at least 8 refreshes to occur.
5. Before issuing the
6. Issue the
action is taken on the SDRAMs. This is normally around 100 µs.
or
Wait the time (determined by t
the
that mode register settings are driven on the SDRAM address bus, so care must be taken to change
DMR[BAM] if the mode register configuration does not fall in the address range determined by
the address mask bits. After the mode register is set, DMR mask bits can be restored to their
desired configuration.
CLKOUT
DRAMW
REF
SRAS
SCAS
SCKE
MRS
Initialization Sequence
commands.
PALL
to execute properly
MRS
command to the SDRAMs by setting DACR[IP] and accessing a SDRAM location.
PALL
command by setting DACR[IMRS] and accessing a location in the SDRAM. Note
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
t
RCD
MRS
= 2
command, determine if the DMR mask bits need to be modified to allow
Figure 15-9. Self-Refresh Operation
SELF
RP
Refresh
) before any other execution.
Active
Self-
SELFX
t
RC
= 6
Synchronous DRAM Controller Module
Possible
ACTV
First
PALL
15-17
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