MCF5281CVM66J Freescale Semiconductor, MCF5281CVM66J Datasheet - Page 305
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MCF5281CVM66J
Manufacturer Part Number
MCF5281CVM66J
Description
IC MPU 256K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5281CVM66J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
150
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF528x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5282-KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5281CVM66J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Freescale Semiconductor
27–25
24–23
21–20
18–17
Bits
22
19
16
START Start transfer.
DSIZE Destination size. Determines the data size of the destination bus cycle for the DMA controller.
SSIZE Source size. Determines the data size of the source bus cycle for the DMA control module.
Name
DINC
BWC
SINC
—
Bandwidth control. Indicates the number of bytes in a block transfer. When the byte count reaches a
multiple of the BWC value, the DMA releases the bus. For example, if BCR24BIT is 0, BWC is 001
(512 bytes or value of 0x0200), and BCR is 0x1000, the bus is relinquished after BCR values of
0x0E00, 0x0C00, 0x0A00, 0x0800, 0x0600, 0x0400, and 0x0200. If BCR24BIT is 0, BWC is 110, and
BCR is 33000, the bus is released after 232 bytes because the BCR is at 32768, a multiple of 16384.
Reserved, should be cleared.
Source increment. Controls whether a source address increments after each successful transfer.
0 No change to SAR after a successful transfer.
1 The SAR increments by 1, 2, 4, or 16, as determined by the transfer size.
00 Longword
01 Byte
10 Word
11 Line (16-byte burst)
Destination increment. Controls whether a destination address increments after each successful
transfer.
0 No change to the DAR after a successful transfer.
1 The DAR increments by 1, 2, 4, or 16, depending upon the size of the transfer.
00 Longword
01 Byte
10 Word
11 Line (16-byte burst)
0 DMA inactive
1 The DMA begins the transfer in accordance to the values in the control registers. START is cleared
automatically after one system clock and is always read as logic 0.
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Table 16-3. DCRn Field Descriptions (continued)
Encoding
000
001
010
011
100
101
110
111
DMA has priority and does not negate its
request until transfer completes.
BCR24BIT = 0
Description
16384
32768
1024
2048
4096
8192
512
BCR24BIT = 1
1048576
131072
262144
524288
16384
32768
65536
DMA Controller Module
16-9
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