MCF5281CVM66J Freescale Semiconductor, MCF5281CVM66J Datasheet - Page 321
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MCF5281CVM66J
Manufacturer Part Number
MCF5281CVM66J
Description
IC MPU 256K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5281CVM66J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
150
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF528x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5282-KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5281CVM66J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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17.4.4
RDAR is a command register, written by the user, indicating the receive descriptor ring is updated (the
driver produced empty receive buffers with the empty bit set).
When the register is written, the RDAR bit is set. This is independent of the data actually written by the
user. When set, the FEC polls the receive descriptor ring and processes receive frames (provided
ECR[ETHER_EN] is also set). After the FEC polls a receive descriptor whose empty bit is not set, FEC
clears the RDAR bit and ceases receive descriptor ring polling until the user sets the bit again, signifying
that additional descriptors are placed into the receive descriptor ring.
The RDAR register is cleared at reset and when ECR[ETHER_EN] is cleared.
Freescale Semiconductor
and
IPSBAR
Figure 17-3
Offset:
Reset
Reset
31–19
Table 17-5
IPSBAR
Field
18–0
See
Offset:
W
W
Reset 0 0 0 0 0 0 0
R
R
0x1008
ERR
W
HB
R 0 0 0 0 0 0 0
31
15
0
0
0
Receive Descriptor Active Register (RDAR)
0x1010
31 30 29 28 27 26 25
Interrupt mask. Each bit corresponds to an interrupt source defined by the EIR register. The corresponding
EIMR bit determines whether an interrupt condition can generate an interrupt. At every processor clock, the
EIR samples the signal generated by the interrupting source. The corresponding EIR bit reflects the state of
the interrupt signal even if the corresponding EIMR bit is set.
0 The corresponding interrupt source is masked.
1 The corresponding interrupt source is not masked.
Reserved, must be cleared.
BABR BABT GRA
30
14
0
0
0
29
13
0
0
0
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Figure 17-4. Receive Descriptor Active Register (RDAR)
Figure 17-3. Ethernet Interrupt Mask Register (EIMR)
28
12
0
0
0
RDAR
24
0
TXF
27
11
0
0
0
Table 17-6. EIMR Field Descriptions
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TXB
26
10
0
0
0
RXF
25
0
0
0
9
RXB
24
0
0
0
8
Description
MII
23
0
0
0
7
ERR
EB
22
0
0
0
6
LC
21
0
0
0
5
RL
20
0
0
0
4
8
Fast Ethernet Controller (FEC)
7
Access: User read/write
UN
19
0
0
0
3
6
Access: User read/write
5
18
4
0
0
2
0
0
3
2
17
0
0
0
0
1
1
0
17-11
16
0
0
0
0
0
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