MCF5281CVM66J Freescale Semiconductor, MCF5281CVM66J Datasheet - Page 692
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MCF5281CVM66J
Manufacturer Part Number
MCF5281CVM66J
Description
IC MPU 256K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5281CVM66J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
150
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF528x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5282-KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5281CVM66J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Electrical Characteristics
33.6
33-8
6
7
8
9
10
11
1
2
3
4
5
6
Analog Supply, with reference to V
Internal Digital Supply
Reference Supply, with reference to V
V
V
V
V
V
V
Maximum Input Current
Load Capacitance determined from crystal manufacturer specifications and will include circuit board parasitics.
This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in the
synthesizer control register (SYNCR).
Assuming a reference is available at power up, lock time is measured from the time V
RSTO negating. If the crystal oscillator is being used as the reference for the PLL, then the crystal start up time
must be added to the PLL lock time to determine the total start-up time.
PLL is operating in 1:1 PLL mode.
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal.
Noise injected into the PLL circuitry via V
Cjitter percentage for a given interval
Based on slow system clock of 40 MHz measured at f
SS
DD
REF
RH
RL
DDH
For internal digital supply of V
Refers to allowed random sequencing of power supplies.
Refers to allowed random sequencing of power supplies.
Transitions within the limit do not affect device reliability or cause permanent damage. Exceeding limit may cause
permanent conversion error on stressed channels and on unstressed channels.
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor,
calculate resistance values using V
calculated values.
Condition applies to one pin at a time.
Differential Voltage
to V
Differential Voltage
to V
Differential Voltage
to V
QADC Electrical Characteristics
SSA
DDA
DDA
Differential Voltage
Differential Voltage
Differential Voltage
Parameter
1
, with reference to V
2
4, 5, 6
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
DD
Table 33-9. QADC Absolute Maximum Ratings
3
SSA
= 3.3V typical.
POSCLAMP
RL
DDPLL
SS
= V
and V
DDA
SSPLL
sys
+ 0.3V and V
V
V
V
V
V
V
DDH
max.
DD
RH
SS
Symbol
RL
RH
V
and variation in crystal oscillator frequency increase the
V
V
I
– V
– V
– V
– V
DDA
MA
DD
RH
– V
– V
SSA
DDA
DDA
SSA
RL
DDA
NEGCLAMP
–0.3
–0.3
–0.3
–0.1
–6.0
–0.3
–6.0
–0.3
–1.0
Min
–25
= –0.3 V, then use the larger of the
DD
and V
Max
6.0
4.0
6.0
0.1
4.0
6.0
6.0
0.3
1.0
25
DDPLL
Freescale Semiconductor
are valid to
Unit
mA
V
V
V
V
V
V
V
V
V
sys
.
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