MCF5281CVM66J Freescale Semiconductor, MCF5281CVM66J Datasheet - Page 165
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MCF5281CVM66J
Manufacturer Part Number
MCF5281CVM66J
Description
IC MPU 256K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5281CVM66J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
150
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF528x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5282-KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5281CVM66J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
- Current page: 165 of 766
- Download datasheet (9Mb)
8.6.3.1
The MPR specifies the access privilege level associated with each bus master in the platform. The register
provides one bit per bus master, where bit 3 corresponds to master 3 (Fast Ethernet Controller, not used on
MCF5216 and MCF5214), bit 2 to master 2 (DMA Controller), bit 1 to master 1 (internal bus master), and
bit 0 to master 0 (ColdFire core).
Only trusted bus masters can modify the access control registers. If a non-trusted bus master attempts to
write any of the SACU control registers, the access is aborted with an error termination and the registers
remain unaffected.
The processor core is connected to bus master 0 and is always treated as a trusted bus master. Accordingly,
MPR[0] is forced to 1 at reset.
8.6.3.2
Access to several on-chip peripherals is controlled by shared peripheral access control registers. A single
PACR defines the access level for each of the two modules. These modules only support operand reads
Freescale Semiconductor
IPSBA
0x03C
0x020
0x024
0x028
0x030
0x034
0x038
Offset
0x02c
R
Bits Name
7–4
3–0
Master Privilege Register (MPR)
Peripheral Access Control Registers (PACR0–PACR8)
[31:28]
MPR
—
Address
GPACR0
PACR0
PACR4
PACR7
MPR
Reset
Field
—
—
—
R/W
Reserved. Should be cleared.
Each 1-bit field defines the access privilege level of the given bus master n.
0 All bus master accesses are in user mode.
1 All bus master accesses use the sourced user/supervisor attribute.
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
[27:24]
7
Figure 8-8. Master Privilege Register (MPR)
Table 8-7. SACU Register Memory Map
Table 8-8. MPR[n] Field Descriptions
[23:20]
—
—
GPACR1
PACR1
—
—
—
—
—
[19:16]
IPSBAR + 0x020
—
0000_0011
Description
R/W
[15:12]
—
PACR2
PACR5
PACR8
MPR[3:0]
—
—
—
—
[11:8]
—
System Control Module (SCM)
0
[7:4]
—
PACR3
PACR6
—
—
—
—
—
[3:0]
—
8-13
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