ST7FLITEUS5B6 STMicroelectronics, ST7FLITEUS5B6 Datasheet - Page 69

• Manufacturer Part Number: ST7FLITEUS5B6
• Description: MCU 8BIT 1KB FLASH 128KB 8-DIP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FLITEUS5B6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 5
• Program Memory Size: 1KB (1K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-DIP (0.300", 7.62mm)
• Controller Family/series: ST7
• No. Of I/o's: 5
• Ram Memory Size: 128Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: 497-6403 - BOARD EVAL 8BIT MICRO + TDE1708497-6407 - BOARD EVAL FOR VACUUM CLEANER497-5861 - EVAL BRD POWER MOSFET/8PIN MCU497-5858 - EVAL BOARD PLAYBACK ST7FLITE497-5515 - EVAL BOARD PHASE CTRL DIMMER497-5049 - KIT STARTER RAISONANCE ST7FLITE497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -
• Other names: 497-5636-5

ST7LITEUS2, ST7LITEUS5
10.1.6
Register description
Lite timer control/status register (LTCSR)
Reset value: 0000 0x00 (0xh)
ICIE
7
Bit 7 ICIE Interrupt Enable.
Bit 6 ICF Input Capture Flag.
Bit 5 TB Timebase period selection.
Bit 4 TBIE Timebase Interrupt enable.
Bit 3 TBF Timebase Interrupt Flag.
ICF
This bit is set and cleared by software.
0: Input Capture (IC) interrupt disabled
1: Input Capture (IC) interrupt enabled
This bit is set by hardware and cleared by software by reading the LTICR register.
Writing to this bit does not change the bit value.
0: No input capture
1: An input capture has occurred
Note: After an MCU reset, software must initialise the ICF bit by reading the LTICR
This bit is set and cleared by software.
0: Timebase period = t
1: Timebase period = t
This bit is set and cleared by software.
0: Timebase (TB) interrupt disabled
1: Timebase (TB) interrupt enabled
This bit is set by hardware and cleared by software reading the LTCSR register.
Writing to this bit has no effect.
0: No counter overflow
1: A counter overflow has occurred
register
TB
OSC
OSC
TBIE
Read / Write
* 8000 (1 ms @ 8 MHz)
* 16000 (2 ms @ 8 MHz)
TBF
WDGR
On-chip peripherals
WDGE
WDGD
0
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