ST7FLITEUS5B6 STMicroelectronics, ST7FLITEUS5B6 Datasheet - Page 66

• Manufacturer Part Number: ST7FLITEUS5B6
• Description: MCU 8BIT 1KB FLASH 128KB 8-DIP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FLITEUS5B6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 5
• Program Memory Size: 1KB (1K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-DIP (0.300", 7.62mm)
• Controller Family/series: ST7
• No. Of I/o's: 5
• Ram Memory Size: 128Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: 497-6403 - BOARD EVAL 8BIT MICRO + TDE1708497-6407 - BOARD EVAL FOR VACUUM CLEANER497-5861 - EVAL BRD POWER MOSFET/8PIN MCU497-5858 - EVAL BOARD PLAYBACK ST7FLITE497-5515 - EVAL BOARD PHASE CTRL DIMMER497-5049 - KIT STARTER RAISONANCE ST7FLITE497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -
• Other names: 497-5636-5

On-chip peripherals
10.1.3
Note:
66/136
Figure 30. Lite timer block diagram
Functional description
The value of the 13-bit counter cannot be read or written by software. After an MCU reset, it
starts incrementing from 0 at a frequency of f
counter rolls over from 1F39h to 00h. If f
counter overflow events is 1 ms. This period can be doubled by setting the TB bit in the
LTCSR register.
When the timer overflows, the TBF bit is set by hardware and an interrupt request is
generated if the TBIE is set. The TBF bit is cleared by software reading the LTCSR register.
Watchdog
The watchdog is enabled using the WDGE bit. The normal watchdog timeout is 2 ms (@
fosc = 8 MHz), after which it then generates a reset.
To prevent this watchdog reset occurring, software must set the WDGD bit. The WDGD bit is
cleared by hardware after t
regular intervals to prevent a watchdog reset occurring. Refer to
If the watchdog is not enabled immediately after reset, the first watchdog timeout will be
shorter than 2ms, because this period is counted starting from reset. Moreover, if a 2ms
period has already elapsed after the last MCU reset, the watchdog reset will take place as
soon as the WDGE bit is set. For these reasons, it is recommended to enable the watchdog
immediately after reset or else to set the WDGD bit before the WGDE bit so a watchdog
reset will not occur for at least 2 ms.
Software can use the timebase feature to set the WDGD bit at 1 or 2 ms intervals.
LTIC
f
OSC
LTICR
13-bit UPCOUNTER
INPUT CAPTURE
REGISTER
8-bit
8 MSB
WDG
7
LTCSR
ICIE
. This means that software must write to the WDGD bit at
f
f
LTIMER
LTIMER
/2
ICF
TB
1
0
OSC
To 12-bit AT TImer
f
WDG
Timebase
1 or 2 ms
(@ 8MHz
f
OSC
TBIE
OSC
= 8 MHz, then the time period between two
)
. A counter overflow event occurs when the
TBF
WDG
RF
WATCHDOG
LTIC INTERRUPT REQUEST
LTTB INTERRUPT REQUEST
WDGE
WDGD
ST7LITEUS2, ST7LITEUS5
Figure
0
WATCHDOG RESET
31.