ST7FLITEUS5B6 STMicroelectronics, ST7FLITEUS5B6 Datasheet - Page 39

• Manufacturer Part Number: ST7FLITEUS5B6
• Description: MCU 8BIT 1KB FLASH 128KB 8-DIP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FLITEUS5B6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 5
• Program Memory Size: 1KB (1K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-DIP (0.300", 7.62mm)
• Controller Family/series: ST7
• No. Of I/o's: 5
• Ram Memory Size: 128Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: 497-6403 - BOARD EVAL 8BIT MICRO + TDE1708497-6407 - BOARD EVAL FOR VACUUM CLEANER497-5861 - EVAL BRD POWER MOSFET/8PIN MCU497-5858 - EVAL BOARD PLAYBACK ST7FLITE497-5515 - EVAL BOARD PHASE CTRL DIMMER497-5049 - KIT STARTER RAISONANCE ST7FLITE497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -
• Other names: 497-5636-5

ST7LITEUS2, ST7LITEUS5
7
Note:
Note:
7.1
Interrupts
The ST7 core may be interrupted by one of two different methods: Maskable hardware
interrupts as listed in the “interrupt mapping” table and a non-maskable software interrupt
(TRAP). The Interrupt processing flowchart is shown in
The maskable interrupts must be enabled by clearing the I bit in order to be serviced.
However, disabled interrupts may be latched and processed when they are enabled (see
external interrupts subsection).
After reset, all interrupts are disabled.
When an interrupt has to be serviced:
●
●
●
●
The interrupt service routine should finish with the IRET instruction which causes the
contents of the saved registers to be recovered from the stack.
As a consequence of the IRET instruction, the I bit is cleared and the main program
resumes.
Priority management
By default, a servicing interrupt cannot be interrupted because the I bit is set by hardware
entering in interrupt routine.
In the case when several interrupts are simultaneously pending, an hardware priority
defines which one will be serviced first (see
Interrupts and low power mode
All interrupts allow the processor to leave the Wait low power mode. Only external and
specifically mentioned interrupts allow the processor to leave the Halt low power mode (refer
to the “Exit from Halt” column in
Non maskable software interrupt
This interrupt is entered when the TRAP instruction is executed regardless of the state of
the I bit. It is serviced according to the flowchart in
Normal processing is suspended at the end of the current instruction execution.
The PC, X, A and CC registers are saved onto the stack.
The I bit of the CC register is set to prevent additional interrupts.
The PC is then loaded with the interrupt vector of the interrupt to service and the first
instruction of the interrupt service routine is fetched (refer to the Interrupt Mapping table
for vector addresses).
Table 9: Interrupt
Table 9: Interrupt
mapping).
Figure
Figure
14.
mapping).
14.
Interrupts
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