AT91SAM9XE256-CU Atmel, AT91SAM9XE256-CU Datasheet - Page 847

• Manufacturer Part Number: AT91SAM9XE256-CU
• Description: MCU ARM9 256K FLASH 217-BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9XE256-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 56K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: 2-Wire, EBI, I2S, SPI, USART
• Maximum Clock Frequency: 180 MHz
• Number Of Programmable I/os: 96
• Number Of Timers: 6
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, KSK-AT91SAM9XE-PL, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9XE-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 4 Channel
• Package: 217LFBGA
• Device Core: ARM926EJ-S
• Family Name: 91S
• Maximum Speed: 180 MHz
• Operating Supply Voltage: 1.8|2.5|3.3 V
• For Use With: AT91SAM9XE-EK - KIT EVAL FOR AT91SAM9XEAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6254C–ATARM–22-Jan-10
Doc.
Rev
6254B
Comments
Overview:
“Features”,
Debug Unit (DBGU), added “mode for general purpose two-sire UART serial communication“
Section 10.4.9 “Ethernet 10/100
Section 9.13 “Chip
Removed former Section 5.2 “Power Consumption”.
Table 3-1, “Signal Description
PIOA - PIOB -
Section 6. “I/O Line
“Features”,
“Features” “Four Universal Synchronous/Asynchronous Receiver Transmitters
Encoding/Decoding,
Section 1. “AT91SAM9XE128/256/512
Section 6.3 “Shutdown Logic
Debug and Test
Section 12.5 “JTAG Port
Boot Program:
Section 13.4.4 “In-Application Programming (IAP)
AIC:
Section 29.6.3 “Interrupt
Section 29.7.5 “Protect
Qualified/Internal on ATP
DBGU:
Section 30.1
ECC:
Section 25.4.3 “ECC Status Register 1”
MULERRx on bitfields, 2, 18, 22, 26, 30.
Section 25.4.1 “ECC Control
EEFC:
Section 20.4.2 “EEFC Flash Command
ISI:
Section 41.4.7 “ISI Preview
PMC:
Section 28.7 “Programming
RSTC:
Section 15.3.4.5 “Software Reset”
“Ethernet MAC 10/100
“Additional Embedded Memories”
“Description”, added to second paragraph; “...two-pin UART can be used as stand-alone...”
PIOC”, has a foot note added to its comments column. SHDWN is active Low.
Identification”, SAM9XE512 chip ID is 0x329AA3A0.
Considerations”, unneeded paragraphs removed.
Mode”, enabling Debug Control Protect Mode in AIC_DCR register updated.
Sources”, Interrupt Source 1, OR-wiring description updated.
Pins”, added to Debug and Test.
Register”, updated PREV_VSIZE and PREV_HSIZE with RGB only comments
Sequence”, steps 5 and 6: “By default PRES parameter is set to 0.....”
Register”, added new bitfield: SRST
Pins”, updated with external pull-up requirement.
List”, comment column updated in certain instances and
MAC”, 128-byte FIFOs (typo corrected).
PERRST must be used with PROCRST, except for debug purposes.
Base-T”, 128-byte FIFOs (typo corrected).
Description”, 2nd and 3rd paragraphs improved.
Register”, updated FARG bit field description
and
AT91SAM9XE128/256/512 Preliminary
Section 25.4.4 “ECC Status Register
Fast Read Time: 45 ns.
Feature”, added to datasheet.
(USART)”, added Manchester
2”, ECCERRx renamed as
“PIO Controller -
Change
Request
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