AT91SAM9XE256-CU Atmel, AT91SAM9XE256-CU Datasheet - Page 148

• Manufacturer Part Number: AT91SAM9XE256-CU
• Description: MCU ARM9 256K FLASH 217-BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9XE256-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 56K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: 2-Wire, EBI, I2S, SPI, USART
• Maximum Clock Frequency: 180 MHz
• Number Of Programmable I/os: 96
• Number Of Timers: 6
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, KSK-AT91SAM9XE-PL, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9XE-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 4 Channel
• Package: 217LFBGA
• Device Core: ARM926EJ-S
• Family Name: 91S
• Maximum Speed: 180 MHz
• Operating Supply Voltage: 1.8|2.5|3.3 V
• For Use With: AT91SAM9XE-EK - KIT EVAL FOR AT91SAM9XEAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

20.3.3
148
AT91SAM9XE128/256/512 Preliminary
Flash Commands
The Enhanced Embedded Flash Controller (EEFC) offers a set of commands such as program-
ming the memory Flash, locking and unlocking lock regions, consecutive programming and
locking and full Flash erasing, etc.
Commands and read operations can be performed in parallel only on different memory planes.
Code can be fetched from one memory plane while a write or an erase operation is performed
on another.
Table 20-1.
In order to perform one of these commands, the Flash Command Register (EEFC_FCR) has to
be written with the correct command using the field FCMD. As soon as the EEFC_FCR register
is written, the FRDY flag and the field FVALUE in the EEFC_FRR register are automatically
cleared. Once the current command is achieved, then the FRDY flag is automatically set. If an
interrupt has been enabled by setting the bit FRDY in EEFC_FMR, the interrupt line of the Sys-
tem Controller is activated.
All the commands are protected by the same keyword, which has to be written in the 8 highest
bits of the EEFC_FCR register.
Writing EEFC_FCR with data that does not contain the correct key and/or with an invalid com-
mand has no effect on the whole memory plane, but the FCMDE flag is set in the EEFC_FSR
register. This flag is automatically cleared by a read access to the EEFC_FSR register.
When the current command writes or erases a page in a locked region, the command has no
effect on the whole memory plane, but the FLOCKE flag is set in the EEFC_FSR register. This
flag is automatically cleared by a read access to the EEFC_FSR register.
Command
Get Flash Descriptor
Write page
Write page and lock
Erase page and write page
Erase page and write page then lock
Erase all
Set Lock Bit
Clear Lock Bit
Get Lock Bit
Set GPNVM Bit
Clear GPNVM Bit
Get GPNVM Bit
Set of Commands
0x5
Value
0x0
0x1
0x2
0x3
0x4
0x8
0x9
0xA
0xB
0xC
0xD
Mnemonic
GETD
WP
WPL
EWP
EWPL
EA
SLB
CLB
GLB
SGPB
CGPB
GGPB
6254C–ATARM–22-Jan-10