ATSAM3S4AA-MU Atmel, ATSAM3S4AA-MU Datasheet - Page 868

• Manufacturer Part Number: ATSAM3S4AA-MU
• Description: IC MCU 32BIT 256KB FLASH 48QFN
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S4AA-MU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 8x10/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Figure 36-15. Comparison Waveform
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Comparison Update
Comparison Match
SAM3S Preliminary
CVMVUPD
CUPRUPD
CUPRCNT
CPRUPD
CTRUPD
CPRCNT
CVUPD
CCNT0
CMPM
CMPU
CUPR
CVM
CPR
CTR
CV
0x6
0x1
0x1
0x3
0x6
0x1
0x1
0x3
0x0
0x0
The update of the comparison x configuration and the comparison x value is triggered periodi-
cally after the comparison x update period. It is defined by the field CUPR in the PWM_CMPxM.
The comparison unit has an update period counter independent from the period counter to trig-
ger this update. When the value of the comparison update period counter CUPRCNT (in
PWM_CMPxM) reaches the value defined by CUPR, the update is triggered. The comparison x
update period CUPR itself can be updated while the channel 0 is enabled by using the
PWM_CMPxMUPD register.
CAUTION: to be taken into account, the write of the register PWM_CMPxVUPD must be fol-
lowed by a write of the register PWM_CMPxMUPD.
The comparison match and the comparison update can be source of an interrupt, but only if it is
enabled and not masked. These interrupts can be enabled by the
ter 2”
and the comparison update interrupt are reset by reading
and disabled by the
0x1
0x1
0x2
0x2
0x0
0x2
0x3
0x2
0x3
0x1
“PWM Interrupt Disable Register 2”
0x2
0x2
0x2
0x0
0x0
0x3
0x1
0x1
0x2
0x2
0x0
0x3
0x6
the“PWM Interrupt Status Register 2”
0x1
0x0
. The comparison match interrupt
0x2
0x1
“PWM Interrupt Enable Regis-
0x6
0x0
0x2
6500C–ATARM–8-Feb-11
0x1
0x3
.