ATSAM3S4AA-MU Atmel, ATSAM3S4AA-MU Datasheet - Page 739

• Manufacturer Part Number: ATSAM3S4AA-MU
• Description: IC MCU 32BIT 256KB FLASH 48QFN
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S4AA-MU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 8x10/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

33.8.15
Name:
Addresses:
Access:
This register can only be written if the WPEN bit is cleared in
• TX_PL: Transmitter Preamble Length
0: The Transmitter Preamble pattern generation is disabled
1 - 15: The Preamble Length is TX_PL x Bit Period
• TX_PP: Transmitter Preamble Pattern
The following values assume that TX_MPOL field is not set:
• TX_MPOL: Transmitter Manchester Polarity
0: Logic Zero is coded as a zero-to-one transition, Logic One is coded as a one-to-zero transition.
1: Logic Zero is coded as a one-to-zero transition, Logic One is coded as a zero-to-one transition.
• RX_PL: Receiver Preamble Length
0: The receiver preamble pattern detection is disabled
1 - 15: The detected preamble length is RX_PL x Bit Period
• RX_PP: Receiver Preamble Pattern detected
The following values assume that RX_MPOL field is not set:
6500C–ATARM–8-Feb-11
6500C–ATARM–8-Feb-11
Value
Value
31
23
15
–
–
–
7
–
00
01
10
11
00
USART Manchester Configuration Register
Name
ALL_ONE
ALL_ZERO
ZERO_ONE
ONE_ZERO
Name
ALL_ONE
DRIFT
30
22
14
US_MAN
0x40024050 (0), 0x40028050 (1)
Read-write
–
–
6
–
Description
The preamble is composed of ‘01’s
Description
The preamble is composed of ‘1’s
The preamble is composed of ‘0’s
The preamble is composed of ‘10’s
The preamble is composed of ‘1’s
29
21
13
1
–
–
5
–
RX_MPOL
TX_MPOL
28
20
12
–
4
–
“USART Write Protect Mode Register” on page
27
19
11
–
–
3
26
18
10
–
–
2
SAM3S Preliminary
SAM3S Preliminary
RX_PL
TX_PL
25
17
9
1
RX_PP
TX_PP
741.
24
16
8
0
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