ATSAM3S4AA-MU Atmel, ATSAM3S4AA-MU Datasheet - Page 1010

• Manufacturer Part Number: ATSAM3S4AA-MU
• Description: IC MCU 32BIT 256KB FLASH 48QFN
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S4AA-MU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 8x10/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

39.7.17
Name:
Address:
Access:
This register can only be written if the WPEN bit is cleared in
• OFFx: Offset for channel x
0 = No Offset.
1 = center the analog signal on Vrefin/2 before the gain scaling. The Offset applied is: (G-1)Vrefin/2
where G is the gain applied (see description of ADC_CGR register).
• DIFFx: Differential inputs for channel x
0 = Single Ended Mode.
1 = Fully Differential Mode.
1010
1010
DIFF15
OFF15
DIFF7
OFF7
31
23
15
7
SAM3S Preliminary
SAM3S Preliminary
ADC Channel Offset Register
DIFF14
OFF14
DIFF6
OFF6
30
22
14
ADC_COR
0x4003804C
Read-write
6
DIFF13
OFF13
DIFF5
OFF5
29
21
13
5
DIFF12
OFF12
DIFF4
OFF4
28
20
12
4
“ADC Write Protect Mode Register” on page
DIFF11
OFF11
DIFF3
OFF3
27
19
11
3
DIFF10
OFF10
DIFF2
OFF2
26
18
10
2
DIFF9
DIFF1
OFF9
OFF1
25
17
9
1
6500C–ATARM–8-Feb-11
6500C–ATARM–8-Feb-11
1013.
DIFF8
DIFF0
OFF8
OFF0
24
16
8
0