ATMEGA64A-AU Atmel, ATMEGA64A-AU Datasheet - Page 46
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ATMEGA64A-AU
Manufacturer Part Number
ATMEGA64A-AU
Description
MCU AVR 64K ISP FLASH 64-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets
1.ATMEGA64A-MUR.pdf
(21 pages)
2.ATMEGA64A-AU.pdf
(392 pages)
3.ATMEGA64A-AU.pdf
(3 pages)
Specifications of ATMEGA64A-AU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Package
64TQFP
Device Core
AVR
Family Name
ATmega
Maximum Speed
16 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
53
Interface Type
SPI/USART
On-chip Adc
8-chx10-bit
Number Of Timers
4
Processor Series
ATMEGA64x
Core
AVR8
Data Ram Size
4 KB
Maximum Clock Frequency
16 MHz
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
Cpu Family
ATmega
Device Core Size
8b
Frequency (max)
16MHz
Total Internal Ram Size
4KB
# I/os (max)
53
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
64
Package Type
TQFP
For Use With
770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA64A-AU
Manufacturer:
ATMEL
Quantity:
4 500
Company:
Part Number:
ATMEGA64A-AU
Manufacturer:
Atmel
Quantity:
900
Company:
Part Number:
ATMEGA64A-AU
Manufacturer:
ATMEL85
Quantity:
900
Part Number:
ATMEGA64A-AU
Manufacturer:
AT
Quantity:
20 000
9. Power Management and Sleep Modes
9.1
9.2
8160C–AVR–07/09
Idle Mode
ADC Noise Reduction Mode
Sleep modes enable the application to shut down unused modules in the MCU, thereby saving
power. The AVR provides various sleep modes allowing the user to tailor the power consump-
tion to the application’s requirements.
To enter any of the six sleep modes, the SE-bit in MCUCR must be written to logic one and a
SLEEP instruction must be executed. The SM2, SM1, and SM0 bits in the MCUCR Register
select which sleep mode (Idle, ADC Noise Reduction, Power-down, Power-save, Standby, or
Extended Standby) will be activated by the SLEEP instruction. See
an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU is
then halted for four cycles in addition to the start-up time, it executes the interrupt routine, and
resumes execution from the instruction following SLEEP. The contents of the Register File and
SRAM are unaltered when the device wakes up from sleep. If a reset occurs during sleep mode,
the MCU wakes up and executes from the Reset Vector.
Figure 8-1 on page 37
bution. This figure is helpful in selecting an appropriate sleep mode.
When the SM2:0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle mode,
stopping the CPU but allowing SPI, USART, Analog Comparator, ADC, Two-wire Serial Inter-
face, Timer/Counters, Watchdog, and the interrupt system to continue operating. This sleep
mode basically halts clk
Idle mode enables the MCU to wake up from external triggered interrupts as well as internal
ones like the Timer Overflow and USART Transmit Complete interrupts. If wake-up from the
Analog Comparator interrupt is not required, the Analog Comparator can be powered down by
setting the ACD bit in the Analog Comparator Control and Status Register – ACSR. This will
reduce power consumption in Idle mode. If the ADC is enabled, a conversion starts automati-
cally when this mode is entered.
When the SM2:0 bits are written to 001, the SLEEP instruction makes the MCU enter ADC
Noise Reduction mode, stopping the CPU but allowing the ADC, the external interrupts, the
Two-wire Serial Interface address watch, Timer/Counter0 and the Watchdog to continue operat-
ing (if enabled). This sleep mode basically halts clk
other clocks to run.
This improves the noise environment for the ADC, enabling higher resolution measurements. If
the ADC is enabled, a conversion starts automatically when this mode is entered. Apart form the
ADC Conversion Complete interrupt, only an External Reset, a Watchdog Reset, a Brown-out
Reset, a Two-wire Serial Interface address match interrupt, a Timer/Counter0 interrupt, an
SPM/EEPROM ready interrupt, an external level interrupt on INT7:4, or an External Interrupt on
INT3:0 can wake up the MCU from ADC Noise Reduction mode.
presents the different clock systems in the ATmega64A, and their distri-
CPU
and clk
FLASH
, while allowing the other clocks to run.
I/O
, clk
CPU
, and clk-
Table 9-2
FLASH
ATmega64A
, while allowing the
for a summary. If
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