ATMEGA64A-AU Atmel, ATMEGA64A-AU Datasheet - Page 273

• Manufacturer Part Number: ATMEGA64A-AU
• Description: MCU AVR 64K ISP FLASH 64-TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64A-AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Package: 64TQFP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 53
• Interface Type: SPI/USART
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 4
• Processor Series: ATMEGA64x
• Core: AVR8
• Data Ram Size: 4 KB
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• Cpu Family: ATmega
• Device Core Size: 8b
• Frequency (max): 16MHz
• Total Internal Ram Size: 4KB
• # I/os (max): 53
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: TQFP
• For Use With: 770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 25-6.
Note:
25.6
8160C–AVR–07/09
Ste
p
1
2
3
4
5
6
7
8
9
10
11
Actions
SAMPLE_PRELOAD
EXTEST
Verify the COMP bit scanned out to be 0
Verify the COMP bit scanned out to be 1
1. Using this algorithm, the timing constraint on the HOLD signal constrains the TCK clock frequency. As the algorithm keeps
ATmega64A Boundary-scan Order
HOLD high for five steps, the TCK clock frequency has to be at least five times the number of scan bits divided by the maxi-
mum hold time, t
Algorithm for Using the ADC
hold,max
As an example, consider the task of verifying a 1.5V ± 5% input signal at ADC channel 3 when
the power supply is 5.0V and AREF is externally connected to V
The recommended values from
rithm in
“Actions” describes what JTAG instruction to be used before filling the Boundary-scan Register
with the succeeding columns. The verification should be done on the data scanned out when
scanning in the data on the same row in the table.
Table 25-7
selected as data path. Bit 0 is the LSB; the first bit scanned in, and the first bit scanned out. The
scan order follows the pinout order as far as possible. Therefore, the bits of Port A are scanned
in the opposite bit order of the other ports. Exceptions from the rules are the scan chains for the
analog circuits, which constitute the most significant bits of the scan chain regardless of which
physical pin they are connected to. In
.
Table
shows the Scan order between TDI and TDO when the Boundary-scan Chain is
25-6. Only the DAC and Port Pin values of the Scan-chain are shown. The column
(1)
The lower limit is:
The upper limit is:
ADCEN
1
1
1
1
1
1
1
1
1
1
1
0x200
0x200
0x200
0x123
0x123
0x200
0x200
0x200
0x143
0x143
0x200
Table 25-5
DAC
1024 1.5V 0,95 5V
Figure
1024 1.5V 1.05 5V
MUXEN
0x08
0x08
0x08
0x08
0x08
0x08
0x08
0x08
0x08
0x08
0x08
⋅
⋅
are used unless other values are given in the algo-
25-3, PXn, Data corresponds to FF0, PXn. Control
⋅
⋅
HOLD
1
0
1
1
1
1
0
1
1
1
1
⁄
⁄
=
PRECH
=
291
323
1
1
1
1
0
1
1
1
1
0
1
CC
=
=
.
0x123
0x143
PA3.
Data
0
0
0
0
0
0
0
0
0
0
0
ATmega64A
Control
PA3.
0
0
0
0
0
0
0
0
0
0
0
Enable
Pull-
PA3.
up_
0
0
0
0
0
0
0
0
0
0
0
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