ATMEGA64A-AU Atmel, ATMEGA64A-AU Datasheet - Page 135

• Manufacturer Part Number: ATMEGA64A-AU
• Description: MCU AVR 64K ISP FLASH 64-TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64A-AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Package: 64TQFP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 53
• Interface Type: SPI/USART
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 4
• Processor Series: ATMEGA64x
• Core: AVR8
• Data Ram Size: 4 KB
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• Cpu Family: ATmega
• Device Core Size: 8b
• Frequency (max): 16MHz
• Total Internal Ram Size: 4KB
• # I/os (max): 53
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: TQFP
• For Use With: 770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 15-5.
Note:
15.11.3
15.11.4
8160C–AVR–07/09
Mode
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
The CTCn and PWMn1:0 bit definition names are obsolete. Use the
tion of these bits are compatible with previous versions of the timer.
WGMn3
TCCR1B – Timer/Counter1 Control Register B
TCCR3B – Timer/Counter3 Control Register B
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Waveform Generation Mode Bit Description
WGMn2
(CTCn)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
• Bit 7 – ICNCn: Input Capture Noise Canceler
Setting this bit (to one) activates the Input Capture Noise Canceler. When the noise canceler is
activated, the input from the Input Capture pin (ICPn) is filtered. The filter function requires four
successive equal valued samples of the ICPn pin for changing its output. The Input Capture is
therefore delayed by four Oscillator cycles when the noise canceler is enabled.
Bit
0x2E (0x4E)
Read/Write
Initial Value
Bit
(0x8A)
Read/Write
Initial Value
(PWMn1)
WGMn1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
ICNC1
ICNC3
R/W
R/W
(PWMn0)
7
0
7
0
WGMn0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
ICES1
ICES3
R/W
R/W
6
0
6
0
Timer/Counter Mode of
Operation
Normal
PWM, Phase Correct, 8-bit
PWM, Phase Correct, 9-bit
PWM, Phase Correct, 10-bit
CTC
Fast PWM, 8-bit
Fast PWM, 9-bit
Fast PWM, 10-bit
PWM, Phase and Frequency
Correct
PWM, Phase and Frequency
Correct
PWM, Phase Correct
PWM, Phase Correct
CTC
(Reserved)
Fast PWM
Fast PWM
R
R
5
–
0
5
–
0
WGM13
WGM33
R/W
R/W
WGM
4
0
4
0
n2:0 definitions. However, the functionality and loca-
WGM12
WGM32
R/W
R/W
3
0
3
0
CS12
CS32
R/W
R/W
ICRn
TOP
0xFFFF
0x00FF
0x01FF
0x03FF
OCRnA
0x00FF
0x01FF
0x03FF
ICRn
OCRnA
OCRnA
ICRn
–
ICRn
OCRnA
2
0
2
0
CS11
CS31
R/W
R/W
1
0
1
0
Update of
OCRn
Immediate
TOP
TOP
TOP
Immediate
BOTTOM
BOTTOM
BOTTOM
BOTTOM
BOTTOM
TOP
TOP
Immediate
–
BOTTOM
BOTTOM
ATmega64A
x
CS10
CS30
R/W
R/W
at
0
0
0
0
TOVn Flag
Set on
MAX
BOTTOM
BOTTOM
BOTTOM
MAX
TOP
TOP
TOP
BOTTOM
BOTTOM
BOTTOM
BOTTOM
MAX
–
TOP
TOP
TCCR1B
TCCR3B
135