ATMEGA64A-AU Atmel, ATMEGA64A-AU Datasheet - Page 389
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ATMEGA64A-AU
Manufacturer Part Number
ATMEGA64A-AU
Description
MCU AVR 64K ISP FLASH 64-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets
1.ATMEGA64A-MUR.pdf
(21 pages)
2.ATMEGA64A-AU.pdf
(392 pages)
3.ATMEGA64A-AU.pdf
(3 pages)
Specifications of ATMEGA64A-AU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Package
64TQFP
Device Core
AVR
Family Name
ATmega
Maximum Speed
16 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
53
Interface Type
SPI/USART
On-chip Adc
8-chx10-bit
Number Of Timers
4
Processor Series
ATMEGA64x
Core
AVR8
Data Ram Size
4 KB
Maximum Clock Frequency
16 MHz
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
Cpu Family
ATmega
Device Core Size
8b
Frequency (max)
16MHz
Total Internal Ram Size
4KB
# I/os (max)
53
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
64
Package Type
TQFP
For Use With
770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA64A-AU
Manufacturer:
ATMEL
Quantity:
4 500
Company:
Part Number:
ATMEGA64A-AU
Manufacturer:
Atmel
Quantity:
900
Company:
Part Number:
ATMEGA64A-AU
Manufacturer:
ATMEL85
Quantity:
900
Part Number:
ATMEGA64A-AU
Manufacturer:
AT
Quantity:
20 000
24 JTAG Interface and On-chip Debug System ...................................... 252
25 IEEE 1149.1 (JTAG) Boundary-scan ................................................... 259
26 Boot Loader Support – Read-While-Write Self-programming ......... 281
8160C–AVR–07/09
23.5
23.6
23.7
23.8
23.9
24.1
24.2
24.3
24.4
24.5
24.6
24.7
24.8
24.9
24.10
25.1
25.2
25.3
25.4
25.5
25.6
25.7
25.8
26.1
26.2
26.3
26.4
26.5
26.6
26.7
26.8
26.9
Prescaling and Conversion Timing ................................................................236
Changing Channel or Reference Selection ...................................................239
ADC Noise Canceler .....................................................................................241
ADC Conversion Result .................................................................................245
Register Description ......................................................................................247
Features ........................................................................................................252
Overview ........................................................................................................252
TAP – Test Access Port ................................................................................252
TAP Controller ...............................................................................................255
Using the Boundary -scan Chain ...................................................................256
Using the On-chip Debug system ..................................................................256
On-chip Debug Specific JTAG Instructions ...................................................257
Using the JTAG Programming Capabilities ...................................................258
On-chip Debug Related Register in I/O Memory ...........................................258
Bibliography ...................................................................................................258
Features ........................................................................................................259
Overview ........................................................................................................259
Data Registers ...............................................................................................259
Boundary-scan Specific JTAG Instructions ...................................................261
Boundary-scan Chain ....................................................................................262
ATmega64A Boundary-scan Order ...............................................................273
Boundary-scan Description Language Files ..................................................280
Boundary-scan Related Register in I/O Memory ...........................................280
Features ........................................................................................................281
Overview ........................................................................................................281
Application and Boot Loader Flash Sections .................................................281
Read-While-Write and No Read-While-Write Flash Sections ........................282
Boot Loader Lock Bits ...................................................................................284
Entering the Boot Loader Program ................................................................285
Addressing the Flash During Self-programming ............................................286
Self-programming the Flash ..........................................................................287
Register Description ......................................................................................293
ATmega64A
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