ATMEGA64A-AU Atmel, ATMEGA64A-AU Datasheet - Page 107

MCU AVR 64K ISP FLASH 64-TQFP

ATMEGA64A-AU

Manufacturer Part Number
ATMEGA64A-AU
Description
MCU AVR 64K ISP FLASH 64-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA64A-AU

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Package
64TQFP
Device Core
AVR
Family Name
ATmega
Maximum Speed
16 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
53
Interface Type
SPI/USART
On-chip Adc
8-chx10-bit
Number Of Timers
4
Processor Series
ATMEGA64x
Core
AVR8
Data Ram Size
4 KB
Maximum Clock Frequency
16 MHz
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
Cpu Family
ATmega
Device Core Size
8b
Frequency (max)
16MHz
Total Internal Ram Size
4KB
# I/os (max)
53
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
64
Package Type
TQFP
For Use With
770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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8160C–AVR–07/09
When OC0 is connected to the pin, the function of the COM01:0 bits depends on the WGM01:0
bit setting.
Normal or CTC mode (non-PWM).
Table 14-3.
Table 14-4
mode.
Table 14-4.
Note:
Table 14-5
rect PWM mode.
Table 14-5.
Note:
• Bit 2:0 – CS02:0: Clock Select
The three Clock Select bits select the clock source to be used by the Timer/Counter, see
14-6.
COM01
COM01
COM01
0
0
1
1
0
0
1
1
0
0
1
1
1. A special case occurs when OCR0 equals TOP and COM01 is set. In this case, the Compare
1. A special case occurs when OCR0 equals TOP and COM01 is set. In this case, the Compare
Table 14-3
Match is ignored, but the set or clear is done at BOTTOM. See
for more details.
Match is ignored, but the set or clear is done at TOP. See
100
shows the COM01:0 bit functionality when the WGM01:0 bits are set to phase cor-
shows the COM01:0 bit functionality when the WGM01:0 bits are set to fast PWM
COM00
Compare Output Mode, non-PWM Mode
Compare Output Mode, Fast PWM Mode
Compare Output Mode, Phase Correct PWM Mode
0
1
0
1
for more details.
COM00
COM00
0
1
0
1
0
1
0
1
shows the COM01:0 bit functionality when the WGM01:0 bits are set to a
Description
Normal port operation, OC0 disconnected.
Reserved.
Clear OC0 on Compare Match when up-counting. Set OC0 on Compare Match
when downcounting.
Set OC0 on Compare Match when up-counting. Clear OC0 on Compare Match
when downcounting.
Description
Normal port operation, OC0 disconnected.
Reserved
Clear OC0 on Compare Match, set OC0 at BOTTOM,
(non-inverting mode).
Set OC0 on Compare Match, clear OC0 at BOTTOM,
(inverting mode).
Description
Normal port operation, OC0 disconnected.
Toggle OC0 on Compare Match.
Clear OC0 on Compare Match.
Set OC0 on Compare Match.
(1)
“Phase Correct PWM Mode” on page
(1)
“Fast PWM Mode” on page 98
ATmega64A
Table
107

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