ATMEGA64A-AU Atmel, ATMEGA64A-AU Datasheet - Page 3

MCU AVR 64K ISP FLASH 64-TQFP

ATMEGA64A-AU

Manufacturer Part Number
ATMEGA64A-AU
Description
MCU AVR 64K ISP FLASH 64-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA64A-AU

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Package
64TQFP
Device Core
AVR
Family Name
ATmega
Maximum Speed
16 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
53
Interface Type
SPI/USART
On-chip Adc
8-chx10-bit
Number Of Timers
4
Processor Series
ATMEGA64x
Core
AVR8
Data Ram Size
4 KB
Maximum Clock Frequency
16 MHz
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
Cpu Family
ATmega
Device Core Size
8b
Frequency (max)
16MHz
Total Internal Ram Size
4KB
# I/os (max)
53
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
64
Package Type
TQFP
For Use With
770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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2. Overview
2.1
Figure 2-1.
8160C–AVR–07/09
AVCC
AREF
PEN
GND
VCC
Block Diagram
ON-CHIP DEBUG
PROGRAMMING
BOUNDARY-
JTAG TAP
Block Diagram
LOGIC
SCAN
DATA REGISTER
DATA REGISTER
PORTE
PORTF
USART0
PORTF DRIVERS
PORTE DRIVERS
PE0 - PE7
PF0 - PF7
The ATmega64A is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC
architecture. By executing powerful instructions in a single clock cycle, the ATmega64A achieves
throughputs approaching 1 MIPS per MHz, allowing the system designer to optimize power con-
sumption versus processing speed.
The AVR core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than con-
ventional CISC microcontrollers.
The ATmega64A provides the following features: 64K bytes of In-System Programmable Flash
with Read-While-Write capabilities, 2K bytes EEPROM, 4K bytes SRAM, 53 general purpose I/O
INSTRUCTION
INSTRUCTION
PROGRAM
COUNTER
PROGRAM
REGISTER
CONTROL
DECODER
FLASH
LINES
ADC
REG. PORTE
REG. PORTF
DATA DIR.
DATA DIR.
REGISTERS
PURPOSE
REGISTER
GENERAL
POINTER
STATUS
STACK
SRAM
DATA REGISTER
DATA REGISTER
ALU
X
Y
Z
PORTA
PORTB
PORTB DRIVERS
PORTA DRIVERS
PA0 - PA7
PB0 - PB7
REG. PORTB
REG. PORTA
DATA DIR.
DATA DIR.
MCU CONTROL
OSCILLATOR
WATCHDOG
COUNTERS
INTERRUPT
REGISTER
INTERNAL
EEPROM
TIMER/
TIMER
UNIT
SPI
DATA REGISTER
DATA REGISTER
PORTC
OSCILLATOR
OSCILLATOR
TIMING AND
CALIB. OSC
CONTROL
PORTD
PORTC DRIVERS
USART1
PC0 - PC7
PORTD DRIVERS
PD0 - PD7
REG. PORTC
DATA DIR.
2-WIRE SERIAL
REG. PORTD
INTERFACE
DATA DIR.
8-BIT DATA BUS
DATA REG.
PORTG
PORTG DRIVERS
ATmega64A
PG0 - PG4
REG. PORTG
DATA DIR.
RESET
XTAL1
XTAL2
3

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