ATMEGA64A-AU Atmel, ATMEGA64A-AU Datasheet - Page 272
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ATMEGA64A-AU
Manufacturer Part Number
ATMEGA64A-AU
Description
MCU AVR 64K ISP FLASH 64-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets
1.ATMEGA64A-MUR.pdf
(21 pages)
2.ATMEGA64A-AU.pdf
(392 pages)
3.ATMEGA64A-AU.pdf
(3 pages)
Specifications of ATMEGA64A-AU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Package
64TQFP
Device Core
AVR
Family Name
ATmega
Maximum Speed
16 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
53
Interface Type
SPI/USART
On-chip Adc
8-chx10-bit
Number Of Timers
4
Processor Series
ATMEGA64x
Core
AVR8
Data Ram Size
4 KB
Maximum Clock Frequency
16 MHz
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
Cpu Family
ATmega
Device Core Size
8b
Frequency (max)
16MHz
Total Internal Ram Size
4KB
# I/os (max)
53
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
64
Package Type
TQFP
For Use With
770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA64A-AU
Manufacturer:
ATMEL
Quantity:
4 500
Company:
Part Number:
ATMEGA64A-AU
Manufacturer:
Atmel
Quantity:
900
Company:
Part Number:
ATMEGA64A-AU
Manufacturer:
ATMEL85
Quantity:
900
Part Number:
ATMEGA64A-AU
Manufacturer:
AT
Quantity:
20 000
8160C–AVR–07/09
Table 25-5.
Note:
If the ADC is not to be used during scan, the recommended input values from
be used. The user is recommended not to use the Differential Gain stages during scan. Switch-
cap based gain stages require fast operation and accurate timing which is difficult to obtain
when used in a scan chain. Details concerning operations of the differential gain stage is there-
fore not provided.
The AVR ADC is based on the analog circuitry shown in
imation algorithm implemented in the digital logic. When used in Boundary-scan, the problem is
usually to ensure that an applied analog voltage is measured within some limits. This can easily
be done without running a successive approximation algorithm: apply the lower limit on the digi-
tal DAC[9:0] lines, make sure the output from the comparator is low, then apply the upper limit
on the digital DAC[9:0] lines, and verify the output from the comparator to be high.
The ADC needs not be used for pure connectivity testing, since all analog inputs are shared with
a digital port pin as well.
When using the ADC, remember the following:
Signal
Name
SCTEST
ST
VCCREN
• The Port Pin for the ADC channel in use must be configured to be an input with pull-up
• In Normal mode, a dummy conversion (consisting of 10 comparisons) is performed when
• The DAC values must be stable at the midpoint value 0x200 when having the HOLD signal
disabled to avoid signal contention.
enabling the ADC. The user is advised to wait at least 200 ns after enabling the ADC before
controlling/observing any ADC signal, or perform a dummy conversion before using the first
result.
low (Sample mode).
1. Incorrect setting of the switches in
the part. There are several input choices to the S&H circuitry on the negative input of the out-
put comparator in
Bandgap reference source, or Ground.
Boundary-scan Signals for the ADC
Input
Input
Direction
as Seen
from the
ADC
Input
Figure
Description
Switch-cap TEST
enable. Output from
x10 gain stage send
out to Port Pin having
ADC_4
Output of gain stages
will settle faster if this
signal is high first two
ACLK periods after
AMPEN goes high.
Selects Vcc as the
ACC reference
voltage.
25-10. Make sure only one path is selected from either one ADC pin,
Figure 25-10
(1)
Recommended
Input when not
(Continued)
will make signal contention and may damage
Figure 25-10
in Use
0
0
0
with a successive approx-
Recommended Inputs
are Used, and CPU is
ATmega64A
Output Values when
not Using the ADC
Table 25-5
0
0
0
should
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