ATMEGA64A-AU Atmel, ATMEGA64A-AU Datasheet - Page 157

• Manufacturer Part Number: ATMEGA64A-AU
• Description: MCU AVR 64K ISP FLASH 64-TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64A-AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Package: 64TQFP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 53
• Interface Type: SPI/USART
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 4
• Processor Series: ATMEGA64x
• Core: AVR8
• Data Ram Size: 4 KB
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• Cpu Family: ATmega
• Device Core Size: 8b
• Frequency (max): 16MHz
• Total Internal Ram Size: 4KB
• # I/os (max): 53
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: TQFP
• For Use With: 770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.9
17.9.1
8160C–AVR–07/09
Register Description
TCCR2 – Timer/Counter Control Register
Figure 17-10. Timer/Counter Timing Diagram, Setting of OCF2, with Prescaler (f
Figure 17-11
Figure 17-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match Mode, with Pres-
• Bit 7 – FOC2: Force Output Compare
The FOC2 bit is only active when the WGM20 bit specifies a non-PWM mode. However, for
ensuring compatibility with future devices, this bit must be set to zero when TCCR2 is written
when operating in PWM mode. When writing a logical one to the FOC2 bit, an immediate Com-
pare Match is forced on the waveform generation unit. The OC2 output is changed according to
its COM21:0 bits setting. Note that the FOC2 bit is implemented as a strobe. Therefore it is the
value present in the COM21:0 bits that determines the effect of the forced compare.
Bit
0x25 (0x45)
Read/Write
Initial Value
TCNTn
TCNTn
(clk
(clk
OCRn
OCRn
(CTC)
OCFn
OCFn
clk
clk
clk
clk
I/O
I/O
I/O
I/O
Tn
Tn
/8)
/8)
shows the setting of OCF2 and the clearing of TCNT2 in CTC mode.
caler (f
FOC2
W
7
0
clk_I/O
WGM20
OCRn - 1
TOP - 1
R/W
6
0
/8)
COM21
R/W
5
0
COM20
R/W
OCRn
4
0
TOP
OCRn Value
WGM21
TOP
R/W
3
0
CS22
R/W
BOTTOM
OCRn + 1
2
0
CS21
R/W
1
0
ATmega64A
BOTTOM + 1
CS20
R/W
OCRn + 2
0
0
clk_I/O
/8)
TCCR2
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