AT32UC3B1256-AUR Atmel, AT32UC3B1256-AUR Datasheet - Page 450

MCU AVR32 256K FLASH 48-TQFP

AT32UC3B1256-AUR

Manufacturer Part Number
AT32UC3B1256-AUR
Description
MCU AVR32 256K FLASH 48-TQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheet

Specifications of AT32UC3B1256-AUR

Package / Case
48-TQFP, 48-VQFP
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Operating Temperature
-40°C ~ 85°C
Speed
60MHz
Number Of I /o
28
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
32K x 8
Program Memory Size
256KB (256K x 8)
Data Converters
A/D 6x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Connectivity
I²C, IrDA, SPI, SSC, UART/USART, USB
Core Size
32-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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22.8.2.18
Register Name:
Access Type:
Offset:
Reset Value:
32059J–12/2010
HSBADDR: HSB Address
31
23
15
7
This field determines the HSB bus current address of a channel transfer.
The address written to the HSB address bus is HSBADDR rounded down to the nearest word-aligned address, i.e.,
Channel HSB start and end addresses may be aligned on any byte boundary.
The user may write this field only when the Channel Enabled bit (CHEN) of the UDDMAnSTATUS register is cleared.
This field is updated at the end of the address phase of the current access to the HSB bus. It is incremented of the HSB access
The HSB access width is 4 bytes, or less at packet start or end if the start or end address is not aligned on a word boundary.
The packet start address is either the channel start address or the next channel address to be accessed in the channel buffer.
The packet end address is either the channel end address or the latest channel address accessed in the channel buffer.
The channel start address is written or loaded from the descriptor, whereas the channel end address is either determined by the
HSBADDR[1:0] is considered as 0b00 since only word accesses are performed.
byte-width.
end of buffer or the end of USB transfer if the Buffer Close Input Enable bit (BUFFCLOSEINEN) is set.
Device DMA Channel n HSB Address Register
30
22
14
6
UDDMAnADDR, n in [1..6]
Read/Write
0x0314 + (n - 1) * 0x10
0x00000000
29
21
13
5
28
20
12
HSBADDR[31:24]
HSBADDR[23:16]
4
HSBADDR[15:8]
HSBADDR[7:0]
27
19
11
3
26
18
10
2
25
17
9
1
AT32UC3B
24
16
8
0
450

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