AT32UC3B1256-AUR Atmel, AT32UC3B1256-AUR Datasheet - Page 440

MCU AVR32 256K FLASH 48-TQFP

AT32UC3B1256-AUR

Manufacturer Part Number
AT32UC3B1256-AUR
Description
MCU AVR32 256K FLASH 48-TQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheet

Specifications of AT32UC3B1256-AUR

Package / Case
48-TQFP, 48-VQFP
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Operating Temperature
-40°C ~ 85°C
Speed
60MHz
Number Of I /o
28
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
32K x 8
Program Memory Size
256KB (256K x 8)
Data Converters
A/D 6x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Connectivity
I²C, IrDA, SPI, SSC, UART/USART, USB
Core Size
32-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT32UC3B1256-AUR
Manufacturer:
OMRON
Quantity:
12 000
Part Number:
AT32UC3B1256-AUR
Manufacturer:
Atmel
Quantity:
10 000
Company:
Part Number:
AT32UC3B1256-AUR
Quantity:
936
32059J–12/2010
CURRBK: Current Bank
NBUSYBK: Number of Busy Banks
DTSEQ: Data Toggle Sequence
SHORTPACKET: Short Packet Interrupt
This bit is set for non-control endpoints, to indicate the current bank:
This field may be updated one clock cycle after the RWALL bit changes, so the user should not poll this field as an interrupt bit.
This field is set to indicate the number of busy banks:
For IN endpoints, it indicates the number of banks filled by the user and ready for IN transfer. When all banks are free, this
For OUT endpoints, it indicates the number of banks filled by OUT transactions from the host. When all banks are busy, this
When the FIFOCON bit is cleared (by writing a one to the FIFOCONC bit) to validate a new bank, this field is updated two or
An EPnINT interrupt is triggered if:
- for IN endpoint, NBUSYBKE is one and all the banks are free.
- for OUT endpoint, NBUSYBKE is one and all the banks are busy.
This field is set to indicate the PID of the current bank:
For IN transfers, it indicates the data toggle sequence that will be used for the next packet to be sent. This is not relative to the
For OUT transfers, this value indicates the last data toggle sequence received on the current bank.
By default DTSEQ is 0b01, as if the last data toggle sequence was Data1, so the next sent or expected data toggle sequence
This bit is set for non-control OUT endpoints, when a short packet has been received.
This bit is set for non-control IN endpoints, a short packet is transmitted upon ending a DMA transfer, thus signaling an end of
This triggers an EPnINT interrupt if SHORTPACKETE is one.
This bit is cleared when the SHORTPACKETC bit is written to one. This will acknowledge the interrupt.
0
0
1
1
0
0
1
1
0
0
1
triggers an EPnINT interrupt if NBUSYBKE is one.
triggers an EPnINT interrupt if NBUSYBKE is one.
three clock cycles later to calculate the address of the next bank.
current bank.
should be Data0.
isochronous frame or a bulk or interrupt end of transfer, this only if the End of DMA Buffer Output Enable (DMAENDEN) bit
and the Automatic Switch (AUTOSW) bit are written to one.
NBUSYBK
CURRBK
DTSEQ
X
0
1
0
1
0
1
0
1
0
1
Current Bank
Bank0
Bank1
Bank2
Reserved
Number of Busy Banks
0 (all banks free)
1
2
3
Data Toggle Sequence
Data0
Data1
Reserved
AT32UC3B
440

Related parts for AT32UC3B1256-AUR