AT32UC3B1256-AUR Atmel, AT32UC3B1256-AUR Datasheet - Page 295

• Manufacturer Part Number: AT32UC3B1256-AUR
• Description: MCU AVR32 256K FLASH 48-TQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3B1256-AUR

• Package / Case: 48-TQFP, 48-VQFP
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 60MHz
• Number Of I /o: 28
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Program Memory Size: 256KB (256K x 8)
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Connectivity: I²C, IrDA, SPI, SSC, UART/USART, USB
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

20.9.13
Name:
Access Type:
Offset:
Reset value:
• RXEN: Receive Enable
• TXEN: Transmit Enable
• RXSYN: Receive Sync
• TXSYN: Transmit Sync
• CP1: Compare 1
• CP0: Compare 0
• OVRUN: Receive Overrun
• RXRDY: Receive Ready
• TXEMPTY: Transmit Empty
32059J–12/2010
31
23
15
7
-
-
-
-
This bit is set when the CR.RXEN bit is written to one.
This bit is cleared when no data are being processed and the CR.RXDIS bit has been written to one.
This bit is set when the CR.TXEN bit is written to one.
This bit is cleared when no data are being processed and the CR.TXDIS bit has been written to one.
This bit is set when a Receive Sync has occurred.
This bit is cleared when the SR register is read.
This bit is set when a Transmit Sync has occurred.
This bit is cleared when the SR register is read.
This bit is set when compare 1 has occurred.
This bit is cleared when the SR register is read.
This bit is set when compare 0 has occurred.
This bit is cleared when the SR register is read.
This bit is set when data has been loaded in the RHR register while previous data has not yet been read.
This bit is cleared when the SR register is read.
This bit is set when data has been received and loaded in the RHR register.
This bit is cleared when the RHR register is empty.
This bit is set when the last data written in the THR register has been loaded in the TSR register and last data loaded in the TSR
register has been transmitted.
Status Register
30
22
14
6
-
-
-
-
SR
Read-only
0x40
0x000000CC
OVRUN
29
21
13
5
-
-
-
RXRDY
28
20
12
4
-
-
-
RXSYN
27
19
11
3
-
-
-
TXSYN
26
18
10
2
-
-
-
TXEMPTY
RXEN
CP1
25
17
9
1
-
AT32UC3B
TXRDY
TXEN
CP0
24
16
8
0
-
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