AT32UC3B1256-AUR Atmel, AT32UC3B1256-AUR Datasheet - Page 19

MCU AVR32 256K FLASH 48-TQFP

AT32UC3B1256-AUR

Manufacturer Part Number
AT32UC3B1256-AUR
Description
MCU AVR32 256K FLASH 48-TQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheet

Specifications of AT32UC3B1256-AUR

Package / Case
48-TQFP, 48-VQFP
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Operating Temperature
-40°C ~ 85°C
Speed
60MHz
Number Of I /o
28
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
32K x 8
Program Memory Size
256KB (256K x 8)
Data Converters
A/D 6x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Connectivity
I²C, IrDA, SPI, SSC, UART/USART, USB
Core Size
32-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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6.3.1
32059J–12/2010
Pipeline Overview
Figure 6-1.
AVR32UC has three pipeline stages, Instruction Fetch (IF), Instruction Decode (ID), and Instruc-
tion Execute (EX). The EX stage is split into three parallel subsections, one arithmetic/logic
(ALU) section, one multiply (MUL) section, and one load/store (LS) section.
Instructions are issued and complete in order. Certain operations require several clock cycles to
complete, and in this case, the instruction resides in the ID and EX stages for the required num-
ber of clock cycles. Since there is only three pipeline stages, no internal data forwarding is
required, and no data dependencies can arise in the pipeline.
Figure 6-2 on page 20
Instruction memory controller
High Speed Bus master
Overview of the AVR32UC CPU
system
shows an overview of the AVR32UC pipeline stages.
OCD
AVR32UC CPU pipeline
MPU
master
Speed
High
Bus
Data memory controller
Bus slave
Speed
High
CPU Local
Power/
control
Reset
master
Bus
AT32UC3B
19

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