ATA6616-P3PW Atmel, ATA6616-P3PW Datasheet - Page 89

• Manufacturer Part Number: ATA6616-P3PW
• Description: TXRX MULTICHIP MOD LIN SIP 38QFN
• Manufacturer: Atmel
• Series: AVR® ATA66 LIN-SBCr

Specifications of ATA6616-P3PW

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 38-VQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.9.3.5
4.9.3.6
4.9.3.7
9132D–AUTO–12/10
Pin Change Interrupt Flag Register – PCIFR
Pin Change Mask Register 1 – PCMSK1
Pin Change Mask Register 0 – PCMSK0
• Bit 7, 2 – Res: Reserved Bits
These bits are unused bits in the Atmel
• Bit 1 - PCIF1: Pin Change Interrupt Flag 1
When a logic change on any PCINT15..8 pin triggers an interrupt request, PCIF1 becomes set
(one). If the I-bit in SREG and the PCIE1 bit in PCICR are set (one), the MCU will jump to the
corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed.
Alternatively, the flag can be cleared by writing a logical one to it.
• Bit 0 - PCIF0: Pin Change Interrupt Flag 0
When a logic change on any PCINT7..0 pin triggers an interrupt request, PCIF0 becomes set
(one). If the I-bit in SREG and the PCIE0 bit in PCICR are set (one), the MCU will jump to the
corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed.
Alternatively, the flag can be cleared by writing a logical one to it.
• Bit 7..0 – PCINT15..8: Pin Change Enable Mask 15..8
Each PCINT15..8-bit selects whether pin change interrupt is enabled on the corresponding I/O
pin. If PCINT15..8 is set and the PCIE1 bit in EIMSK is set, pin change interrupt is enabled on
the corresponding I/O pin. If PCINT15..8 is cleared, pin change interrupt on the corresponding
I/O pin is disabled.
• Bit 7..0 – PCINT7..0: Pin Change Enable Mask 7..0
Each PCINT7..0 bit selects whether pin change interrupt is enabled on the corresponding I/O
pin. If PCINT7..0 is set and the PCIE0 bit in EIMSK is set, pin change interrupt is enabled on
the corresponding I/O pin. If PCINT7..0 is cleared, pin change interrupt on the corresponding
I/O pin is disabled.
Read/Write
Initial Value
Read/Write
Initial Value
Read/Write
Initial Value
Bit
Bit
Bit
PCINT15 PCINT14 PCINT13 PCINT12 PCINT11 PCINT10
PCINT7
R/W
R/W
R
7
0
7
–
0
7
0
PCINT6
R/W
R/W
R
6
–
0
6
0
6
0
PCINT5
R/W
R/W
R
5
–
0
5
0
5
0
®
ATtiny87/167, and will always read as zero.
PCINT4
R/W
R/W
R
4
–
0
4
0
4
0
Atmel ATA6616/ATA6617
PCINT3
R/W
R/W
R
3
–
0
3
0
3
0
PCINT2
R/W
R/W
R
2
–
0
2
0
2
0
PCINT1
PCINT9
PCIF1
R/W
R/W
R/W
1
0
1
0
1
0
PCINT0
PCINT8
PCIF0
R/W
R/W
R/W
0
0
0
0
0
0
PCMSK1
PCMSK0
PCIFR
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