ATA6616-P3PW Atmel, ATA6616-P3PW Datasheet - Page 182

• Manufacturer Part Number: ATA6616-P3PW
• Description: TXRX MULTICHIP MOD LIN SIP 38QFN
• Manufacturer: Atmel
• Series: AVR® ATA66 LIN-SBCr

Specifications of ATA6616-P3PW

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 38-VQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.15.5.3
182
Atmel ATA6616/ATA6617
USISR – USI Status Register
The Status Register contains Interrupt Flags, line Status Flags and the counter value.
• Bit 7 – USISIF: Start Condition Interrupt Flag
When Two-wire mode is selected, the USISIF Flag is set (to one) when a start condition is
detected. When output disable mode or Three-wire mode is selected and (USICSx = 11
USICLK = 0) or (USICS = 10
An interrupt will be generated when the flag is set while the USISIE bit in USICR and the
Global Interrupt Enable Flag are set. The flag will only be cleared by writing a logical one to the
USISIF bit. Clearing this bit will release the start detection hold of USCL in Two-wire mode.
A start condition interrupt will wakeup the processor from all sleep modes.
• Bit 6 – USIOIF: Counter Overflow Interrupt Flag
This flag is set (one) when the 4-bit counter overflows (i.e., at the transition from 15 to 0). An
interrupt will be generated when the flag is set while the USIOIE bit in USICR and the Global
Interrupt Enable Flag are set. The flag will only be cleared if a one is written to the USIOIF bit.
Clearing this bit will release the counter overflow hold of SCL in Two-wire mode.
A counter overflow interrupt will wakeup the processor from Idle sleep mode.
• Bit 5 – USIPF: Stop Condition Flag
When Two-wire mode is selected, the USIPF Flag is set (one) when a stop condition is
detected. The flag is cleared by writing a one to this bit. Note that this is not an Interrupt Flag.
This signal is useful when implementing Two-wire bus master arbitration.
• Bit 4 – USIDC: Data Output Collision
This bit is logical one when bit 7 in the USI Data Register differs from the physical pin value.
The flag is only valid when Two-wire mode is used. This signal is useful when implementing
Two-wire bus master arbitration.
• Bits 3:0 – USICNT3..0: Counter Value
These bits reflect the current 4-bit counter value. The 4-bit counter value can directly be read
or written by the CPU.
The 4-bit counter increments by one for each clock generated either by the external clock
edge detector, by a Timer/Counter0 Compare Match, or by software using USICLK or USITC
strobe bits. The clock source depends of the setting of the USICS1..0 bits. For external clock
operation a special feature is added that allows the clock to be generated by writing to the
USITC strobe bit. This feature is enabled by write a one to the USICLK bit while setting an
external clock source (USICS1 = 1).
Note that even when no wire mode is selected (USIWM1..0 = 0) the external clock input
(USCK/SCL) are can still be used by the counter.
Bit
Read/Write
Initial Value
USISIF
R/W
7
0
USIOIF
R/W
6
0
b
& USICLK = 0), any edge on the SCK pin sets the flag.
USIPF
R/W
5
0
USIDC
R
4
0
USICNT3 USICNT2 USICNT1 USICNT0 USISR
R/W
3
0
R/W
2
0
R/W
1
0
R/W
9132D–AUTO–12/10
0
0
b
&