ATA6616-P3PW Atmel, ATA6616-P3PW Datasheet - Page 120

• Manufacturer Part Number: ATA6616-P3PW
• Description: TXRX MULTICHIP MOD LIN SIP 38QFN
• Manufacturer: Atmel
• Series: AVR® ATA66 LIN-SBCr

Specifications of ATA6616-P3PW

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 38-VQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.11.8
120
Atmel ATA6616/ATA6617
Timer/Counter Timing Diagrams
The PWM waveform is generated by clearing (or setting) the OC0A Register at the compare
match between OCR0A and TCNT0 when the counter increments, and setting (or clearing)
the OC0A Register at compare match between OCR0A and TCNT0 when the counter decre-
ments. The PWM frequency for the output when using phase correct PWM can be calculated
by the following equation:
The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).
The extreme values for the OCR0A Register represent special cases when generating a PWM
waveform output in the phase correct PWM mode. If the OCR0A is set equal to BOTTOM, the
output will be continuously low and if set equal to MAX the output will be continuously high for
non-inverted PWM mode. For inverted PWM the output will have the opposite logic values.
The following figures show the Timer/Counter in synchronous mode, and the timer clock
(clk
replaced by the Timer/Counter Oscillator clock. The figures include information on when inter-
rupt flags are set.
figure shows the count sequence close to the MAX value in all modes other than phase correct
PWM mode.
Figure 4-37. Timer/Counter Timing Diagram, no Prescaling
Figure 4-38
Figure 4-38. Timer/Counter Timing Diagram, with Prescaler (f
f
OCnxPCPWM
T0
TCNTn
TCNTn
(clk
(clk
TOVn
TOVn
clk
clk
clk
clk
) is therefore shown as a clock enable signal. In asynchronous mode, clk
I/O
I/O
I/O
I/O
Tn
Tn
/1)
/8)
=
shows the same timing data, but with the prescaler enabled.
-------------------- -
N
f
clk_I/O
510
Figure 4-37
MAX - 1
MAX - 1
contains timing data for basic Timer/Counter operation. The
MAX
MAX
BOTTOM
BOTTOM
clk_I/O
/8)
BOTTOM + 1
BOTTOM + 1
9132D–AUTO–12/10
I/O
should be