ATA6616-P3PW Atmel, ATA6616-P3PW Datasheet - Page 80

• Manufacturer Part Number: ATA6616-P3PW
• Description: TXRX MULTICHIP MOD LIN SIP 38QFN
• Manufacturer: Atmel
• Series: AVR® ATA66 LIN-SBCr

Specifications of ATA6616-P3PW

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 38-VQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.7.3.3
80
Atmel ATA6616/ATA6617
Watchdog Timer Control Register - WDTCR
• Bit 7 - WDIF: Watchdog Interrupt Flag
This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is con-
figured for interrupt. WDIF is cleared by hardware when executing the corresponding interrupt
handling vector. Alternatively, WDIF is cleared by writing a logic one to the flag. When the I-bit
in SREG and WDIE are set, the Watchdog Time-out Interrupt is executed.
• Bit 6 - WDIE: Watchdog Interrupt Enable
When this bit is written to one and the I-bit in the Status Register is set, the Watchdog Interrupt
is enabled. If WDE is cleared in combination with this setting, the Watchdog Timer is in Inter-
rupt Mode, and the corresponding interrupt is executed if time-out in the Watchdog Timer
occurs.
If WDE is set, the Watchdog Timer is in Interrupt and System Reset Mode. The first time-out in
the Watchdog Timer will set WDIF. Executing the corresponding interrupt vector will clear
WDIE and WDIF automatically by hardware (the Watchdog goes to System Reset Mode). This
is useful for keeping the Watchdog Timer security while using the interrupt. To stay in Interrupt
and System Reset Mode, WDIE must be set after each interrupt. This should however not be
done within the interrupt service routine itself, as this might compromise the safety-function of
the Watchdog System Reset mode. If the interrupt is not executed before the next time-out, a
System Reset will be applied.
If the Watchdog Timer is used as clock monitor (c.f.
trol Bits 3 - 0” on page
automatically disabled.
Table 4-18.
• Bit 4 - WDCE: Watchdog Change Enable
This bit is used in timed sequences for changing WDE and prescaler bits. To clear the WDE
bit, and/or change the prescaler bits, WDCE must be set.
Once written to one, hardware will clear WDCE after four clock cycles.
Note:
Bit
Read/Write
Initial Value
Monitor
Clock
On
Off
x
1. At least one of these three enables (WDTON, WDE & WDIE) equal to 1
WDTON
Watchdog Timer Configuration
WDIF
R/W
y
0
0
0
0
1
7
0
(1)
WDE
WDIE
64), the System Reset Mode is enabled and the Interrupt Mode is
R/W
y
0
0
1
1
x
6
0
(1)
WDIE Mode
WDP3
y
0
1
0
1
x
R/W
(1)
5
0
Stopped
System Reset Mode
Interrupt Mode
System Reset Mode
Interrupt and System Reset
Mode
System Reset Mode
WDCE
R/W
4
0
WDE
R/W
Section • “Bits 3:0 – CLKC3:0: Clock Con-
X
3
WDP2
R/W
2
0
Action on Time-out
None
Reset
Interrupt
Reset
Interrupt, then go to System
Reset Mode
Reset
WDP1
R/W
1
0
WDP0
R/W
0
9132D–AUTO–12/10
0
WDTCR