ATA6616-P3PW Atmel, ATA6616-P3PW Datasheet - Page 171

• Manufacturer Part Number: ATA6616-P3PW
• Description: TXRX MULTICHIP MOD LIN SIP 38QFN
• Manufacturer: Atmel
• Series: AVR® ATA66 LIN-SBCr

Specifications of ATA6616-P3PW

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 38-VQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.14.2.4
4.14.2.5
4.14.3
9132D–AUTO–12/10
Data Modes
SPI Status Register – SPSR
SPI Data Register – SPDR
• Bit 7 – SPIF: SPI Interrupt Flag
When a serial transfer is complete, the SPIF flag is set. An interrupt is generated if SPIE in
SPCR is set and global interrupts are enabled. If SS is an input and is driven low when the SPI
is in Master mode, this will also set the SPIF flag. SPIF is cleared by hardware when executing
the corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first read-
ing the SPI Status Register with SPIF set, then accessing the SPI Data Register (SPDR).
• Bit 6 – WCOL: Write COLlision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer. The
WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status Register with WCOL
set, and then accessing the SPI Data Register.
• Bit 5..1 – Res: Reserved Bits
These bits are reserved bits in the Atmel
• Bit 0 – SPI2X: Double SPI Speed Bit
When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the
SPI is in Master mode (see
CPU clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to work at
f
The SPI interface on the Atmel
downloading or uploading. See
programming and verification.
• Bits 7:0 - SPD7:0: SPI Data
The SPI Data Register is a read/write register used for data transfer between the Register File
and the SPI Shift Register. Writing to the register initiates data transmission. Reading the reg-
ister causes the Shift Register Receive buffer to be read.
There are four combinations of SCK phase and polarity with respect to serial data, which are
determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in
ure 4-60
SCK signal, ensuring sufficient time for data signals to stabilize. This is clearly seen by sum-
marizing
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
clkio
/4 or lower.
Table 4-41
and
Figure
SPD7
SPIF
R/W
X
R
7
7
0
and
4-61. Data bits are shifted out and latched in on opposite edges of the
WCOL
SPD6
R/W
Table
X
R
6
6
0
Table
®
4-42, as done below:
ATtiny87/167 is also used for program memory and EEPROM
SPD5
Section 4.22.8 “Serial Downloading” on page 262
R/W
4-43). This means that the minimum SCK period will be two
5
X
R
5
–
0
®
SPD4
R/W
ATtiny87/167 and will always read as zero.
X
4
R
4
–
0
Atmel ATA6616/ATA6617
SPD3
R/W
X
3
R
3
–
0
SPD2
R/W
X
2
R
2
–
0
SPD1
R/W
X
1
R
1
–
0
SPD0
SPI2X
R/W
R/W
X
0
0
0
SPDR
Undefined
SPSR
for serial
Fig-
171