HD6417708SF60V Renesas Electronics America, HD6417708SF60V Datasheet - Page 79

• Manufacturer Part Number: HD6417708SF60V
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417708SF60V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: EBI/EMI, SCI, SmartCard
• Peripherals: POR, WDT
• Number Of I /o: 8
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -

The MMU registers are shown in figure 3.3.
RC: A 2-bit random counter, automatically updated by hardware according to the
SV: Single virtual memory mode bit. Set to 1 for single virtual memory mode, cleared
AT: Address translation bit. Enables/disables the MMU.
TF: TLB flush bit. Write 1 to flush the TLB (clear all valid bits of the TLB to 0). Always
IX: Index mode bit. When 0, VPN bits 16–12 are used as the TLB index number.
0: Reserved bits (except MMUCR): Always read as 0. Writing is ignored.
to 0 for multiple virtual memory mode.
following rules in the event of an MMU exception. When a TLB miss exception
occurs, all TLB entry ways corresponding to the virtual address at which the
exception occurred are checked, and if all ways are valid, 1 is added to RC; if
there is one or more invalid way, they are set by priority from way 0, in the order:
way 0, way 1, way 2, way 3. In the event of an MMU exception other than a TLB
miss exception, the way which caused the exception is set in RC.
reads 0.
When 1, the value obtained by EX-ORing ASID bits 4–0 in PTEH and VPN bits
16–12 are used as the TLB index number.
0: MMU disabled
31
31
31
31
31
(MMUCR) :Except bit 3 is read as 0. Bit 3 is don't care. Writing is
Virtual address causing TLB-related
Figure 3.3 MMU Register Contents
PPN
or address error exception
0
VPN
should be 0.
MMUCR
PTEH
PTEL
TTB
TTB
TEA
10
10
9
0
8
SV
8
V
0
7
0
7
00
7
PR SZ C D
6 5
6 4 3 2 1 0
RC
4
ASID
3 2 1
0 TF IX AT
SH 0
0
0
0
0
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