HD6417708SF60V Renesas Electronics America, HD6417708SF60V Datasheet - Page 392

• Manufacturer Part Number: HD6417708SF60V
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417708SF60V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: EBI/EMI, SCI, SmartCard
• Peripherals: POR, WDT
• Number Of I /o: 8
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -

Figure 13.6 shows an example of SCI transmit operation in asynchronous mode.
Receiving Serial Data (Asynchronous Mode): Figure 13.7 shows a sample flowchart for
receiving serial data. The procedure for receiving serial data after enabling the SCI for reception
is:
1. Receive error handling and break detection: If a receive error occurs, read the ORER, PER and
2. SCI status check and receive-data read: Read the serial status register (SCSSR), check that
3. To continue receiving serial data: Read the RDRF and SCRDR bits and clear RDRF to 0
372
Figure 13.6 SCI Transmit Operation in Asynchronous Mode (Example: 8-Bit Data with
FER bits in SCSSR to identify the error. After executing the necessary error handling, clear
ORER, PER and FER all to 0. Receiving cannot resume if ORER, PER or FER remain set to 1.
When a framing error occurs, the RxD pin can be read to detect the break state.
RDRF is set to 1, then read receive data from the receive data register (SCRDR) and clear
RDRF to 0. The RXI interrupt can also be used to determine if the RDRF bit has changed from
0 to 1.
before the stop bit of the current frame is received.
TXI interrupt
TDRE
TEND
Serial
request
data
1
Start
bit
0
and clears TDRE
data to SCTDR
handler writes
TXI interrupt
D
bit to 0
0
D
1 frame
1
Data
Parity and One Stop Bit)
D
7
TXI interrupt
Parity
request
bit
0/1
Stop
bit
1
Start
bit
0
D
0
D
1
Data
D
7
Parity
bit
TEI interrupt
0/1
request
Stop
bit
1
(mark)
state
Idle
1