HD6417708SF60V Renesas Electronics America, HD6417708SF60V Datasheet - Page 113
HD6417708SF60V
Manufacturer Part Number
HD6417708SF60V
Description
IC SUPERH MPU ROMLESS 208LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417708SF60V.pdf
(635 pages)
Specifications of HD6417708SF60V
Core Processor
SH-2
Core Size
32-Bit
Speed
60MHz
Connectivity
EBI/EMI, SCI, SmartCard
Peripherals
POR, WDT
Number Of I /o
8
Program Memory Type
ROMless
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
208-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Ram Size
-
Program Memory Size
-
Data Converters
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417708SF60V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD6417708SF60V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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Reserved instruction exception
a. When undefined code not in a delay slot is decoded
b. When a privileged instruction not in a delay slot is decoded in user mode
Illegal slot instruction
a. When undefined code in a delay slot is decoded
b. When an instruction that rewrites the PC in a delay slot is decoded
c. When a privileged instruction in a delay slot is decoded in user mode
User break point trap
Conditions:
Operations: The PC and SR of the instruction that generated the exception are saved to the
Conditions:
Operations: The PC of the previous delay branch instruction is saved to the SPC. SR of the
Conditions: When a break condition set in the user break point controller is satisfied
Operations: When a post-execution break occurs, the PC of the instruction immediately
Delay branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S
Undefined instructions: H'Fxxx(SH7708, SH7708S), H'FxxF(SH7708R)
Privileged instructions: LDC, STC, RTE, LDTLB, SLEEP; instructions that access GBR
with LDC/STC are not privileged instructions
SPC and SSR, respectively. H'180 is set in EXPEVT. The BL, MD, and RB bits in SR are
set to 1 and a branch occurs to PC = VBR + H'0100. When an undefined instruction other
than H'Fxxx is decoded, operation cannot be guaranteed.
Delay branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S
Undefined instructions: H'Fxxx(SH7708, SH7708S), H'FxxF(SH7708R)
Instructions that rewrite the PC: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT, BF,
BT/S, BF/S, TRAPA, LDC Rm, SR, LDC.L, @Rm+, SR
Privileged instructions: LDC, STC, RTE, LDTLB, SLEEP; instructions that access GBR
with LDC/STC are not privileged instructions
instruction that generated the exception is saved to SSR. H'1A0 is set in EXPEVT. The BL,
MD, and RB bits in SR are set to 1 and a branch occurs to PC = VBR + H'0100. When an
undefined instruction other than H'Fxxx is decoded, operation cannot be guaranteed.
after the instruction that set the break point is set in the SPC. If a pre-execution break
occurs, the PC of the instruction that set the break point is set in the SPC. SR when the
break occurs is set in SSR. H'1E0 is set in EXPEVT. The BL, MD, and RB bits in SR are
set to 1 and a branch occurs to PC = VBR + H'0100. See section 7, User Break Controller,
for more information.
93
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