HD6417708SF60V Renesas Electronics America, HD6417708SF60V Datasheet - Page 24
HD6417708SF60V
Manufacturer Part Number
HD6417708SF60V
Description
IC SUPERH MPU ROMLESS 208LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417708SF60V.pdf
(635 pages)
Specifications of HD6417708SF60V
Core Processor
SH-2
Core Size
32-Bit
Speed
60MHz
Connectivity
EBI/EMI, SCI, SmartCard
Peripherals
POR, WDT
Number Of I /o
8
Program Memory Type
ROMless
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
208-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Ram Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417708SF60V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD6417708SF60V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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Table 1.1
Item
Bus state
controller
(BSC)
Timer
Realtime clock
(RTC)
Serial communi-
cation interface
(SCI)
Package
Note: * SH7708S only
4
SH7708 Series Features (cont)
Features
Supports external memory access
Physical address space divided into seven areas, each a maximum 64
Mbytes, with the following features settable for each area:
DRAM/synchronous DRAM/pseudo-SRAM refresh function
DRAM/synchronous DRAM/pseudo-SRAM burst access function
Usable as either big- or little-endian machine
3-channel auto-reload type 32-bit timer
Input capture function
6 types of counter input clock can be selected
Maximum resolution: 2 MHz
On-chip clock and calendar functions
On-chip 32-kHz crystal oscillator circuit with a maximum resolution (interrupt
cycle) of 1/256 second
Selection of asynchronous or synchronous mode
Full-duplex communication
Supports smart card interface
144-pin plastic QFP(FP-144)
144-pin plastic TQFP (TFP-144)*
32/16/8-bit external data bus
Bus size (8, 16, or 32 bits)
Number of wait cycles (also supports a hardware wait function)
Setting the type of space enables direct connection to DRAM,
Supports fast page mode and EDO for DRAM
Supports PCMCIA interface
Outputs chip select signal (CS0–CS6) for corresponding area
Programmable refresh interval
Supports CAS-before-RAS refresh and self-refresh modes
synchronous DRAM, pseudo-SRAM, and burst ROM
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