HD6417708SF60V Renesas Electronics America, HD6417708SF60V Datasheet - Page 141
HD6417708SF60V
Manufacturer Part Number
HD6417708SF60V
Description
IC SUPERH MPU ROMLESS 208LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417708SF60V.pdf
(635 pages)
Specifications of HD6417708SF60V
Core Processor
SH-2
Core Size
32-Bit
Speed
60MHz
Connectivity
EBI/EMI, SCI, SmartCard
Peripherals
POR, WDT
Number Of I /o
8
Program Memory Type
ROMless
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
208-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Ram Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417708SF60V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD6417708SF60V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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Table 6.6
Item
Response
time
Icyc:
Bcyc: Duration of one CKIO cycle
Pcyc: Duration of one cycle of peripheral clock supplied to supporting modules
Notes: 1. S also includes the memory access wait time.
Duration of one cycle of internal clock supplied to CPU, etc.
2. The internal clock : CKIO : peripheral clock ratio is 1 : 1 : 1.
3. The internal clock : CKIO : peripheral clock ratio is 1 : 1 : 1/4.
The processing requiring the maximum execution time is LDC.L @Rm+, SR. When the
memory access is a cache-hit, this requires 7 instruction execution cycles. When
external access is performed, the corresponding number of cycles must be added.
There are also instructions that perform two external memory accesses; if external
memory access is slow, the number of instruction execution cycles will increase
accordingly.
Total
Minimum
case*
Maximum
case*
Interrupt Response Time (cont)
2
3
NMI
(5.5 + X)
+ 0.5
+ 0.5
6.5
7 + S
Bcyc
Pcyc
Icyc
Number of States
RL
(5.5 + X)
+ 0.5
+ 2
8
13 + S
Pcyc
Bcyc
Icyc
Peripheral
Modules
(5.5 + X)
+ 1.5
7
10.5 + S
Pcyc
Icyc
Notes
At 60 MHz operation:
0.10–0.14 µs
At 60 MHz operation:
0.23–0.34 µs (in case of
operand cache-hit)
At 60 MHz operation:
0.27–0.37 µs (when
external memory access
is performed with wait =
0)
121
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