HD6417708SF60V Renesas Electronics America, HD6417708SF60V Datasheet - Page 12
HD6417708SF60V
Manufacturer Part Number
HD6417708SF60V
Description
IC SUPERH MPU ROMLESS 208LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417708SF60V.pdf
(635 pages)
Specifications of HD6417708SF60V
Core Processor
SH-2
Core Size
32-Bit
Speed
60MHz
Connectivity
EBI/EMI, SCI, SmartCard
Peripherals
POR, WDT
Number Of I /o
8
Program Memory Type
ROMless
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
208-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Ram Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417708SF60V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD6417708SF60V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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3.4
3.5
3.6
3.7
Section 4 Exception Handling
4.1
4.2
4.3
4.4
4.5
4.6
Section 5 Cache
5.1
ii
3.3.4
MMU Functions ................................................................................................................ 66
3.4.1
3.4.2
3.4.3
3.4.4
MMU Exceptions .............................................................................................................. 70
3.5.1
3.5.2
3.5.3
3.5.4
3.5.5
Memory-Mapped TLB ...................................................................................................... 77
3.6.1
3.6.2
3.6.3
Usage Note ........................................................................................................................ 80
Overview............................................................................................................................ 81
4.1.1
4.1.2
Exception Handling Function............................................................................................ 81
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
4.2.6
Register Description .......................................................................................................... 88
Exception Handler Operation ............................................................................................ 89
4.4.1
4.4.2
4.4.3
Individual Exception Operations ....................................................................................... 90
4.5.1
4.5.2
4.5.3
Cautions ............................................................................................................................. 95
Overview............................................................................................................................ 97
Page Management Information ............................................................................ 65
MMU Hardware Management ............................................................................. 66
MMU Software Management............................................................................... 66
MMU Instruction (LDLTB) ................................................................................. 67
Avoiding Synonym Problems .............................................................................. 68
TLB Miss Exception ............................................................................................ 70
TLB Protection Violation Exception.................................................................... 71
TLB Invalid Exception ......................................................................................... 72
Initial Page Write Exception ................................................................................ 73
Processing Flow in Event of MMU Exception
(Same Processing Flow for Address Error).......................................................... 75
Address Array ...................................................................................................... 77
Data Array ............................................................................................................ 78
Usage Examples ................................................................................................... 80
Features ................................................................................................................ 81
Register Configuration ......................................................................................... 81
Exception Handling Flow..................................................................................... 81
Exception Handling Vector Addresses ................................................................ 82
Acceptance of Exceptions .................................................................................... 84
Exception Codes................................................................................................... 86
Exception Request Masks .................................................................................... 87
Returning from Exception Handling .................................................................... 88
Reset ..................................................................................................................... 89
Interrupts .............................................................................................................. 89
General Exceptions .............................................................................................. 89
Resets.................................................................................................................... 90
General Exceptions .............................................................................................. 91
Interrupts .............................................................................................................. 94
.................................................................................................................... 97
.......................................................................................... 81
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