HD6417708SF60V Renesas Electronics America, HD6417708SF60V Datasheet - Page 416

• Manufacturer Part Number: HD6417708SF60V
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417708SF60V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: EBI/EMI, SCI, SmartCard
• Peripherals: POR, WDT
• Number Of I /o: 8
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -

The receive margin in the asynchronous mode can therefore be expressed as shown in equation 1.
Equation 1:
Where:
M = Receive margin (%)
N = Ratio of clock frequency to bit rate (N = 16)
D = Clock duty cycle (D = 0–1.0)
L = Frame length (L = 9–12)
F = Absolute deviation of clock frequency
From equation (1), if F = 0 and D = 0.5, the receive margin is 46.875%, as shown in equation 2.
Equation 2:
This is a theoretical value. A reasonable margin to allow in system designs is 20–30%.
396
Base clock
data (RxD)
Synchro-
sampling
sampling
Receive
nization
timing
timing
M = (0.5 – 1/(2
M = 0.5 –
Data
Figure 13.21 Receive Data Sampling Timing in Asynchronous Mode
= 46.875%
0 1 2 3 4 5 6 7 8 9 10111213 1415 0 1 2 3 4 5 6 7 8 9 10111213 1415 0 1 2 3 4 5
8 clock cycles
2N
1
Start bit
– (L – 0.5)F –
16 clock cycles
16))
100%
–7.5 clock
cycles
D – 0.5
N
(1 + F)
+7.5 clock
cycles
100%
D0
D1