HD6417708SF60V Renesas Electronics America, HD6417708SF60V Datasheet - Page 110
HD6417708SF60V
Manufacturer Part Number
HD6417708SF60V
Description
IC SUPERH MPU ROMLESS 208LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417708SF60V.pdf
(635 pages)
Specifications of HD6417708SF60V
Core Processor
SH-2
Core Size
32-Bit
Speed
60MHz
Connectivity
EBI/EMI, SCI, SmartCard
Peripherals
POR, WDT
Number Of I /o
8
Program Memory Type
ROMless
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
208-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Ram Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417708SF60V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD6417708SF60V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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4.5
This section describes the conditions for specific exception handling, and the processor operations.
4.5.1
Table 4.4
Type
Power-on
reset
Manual
reset
90
The RB bit in SR is set to 1.
An encoded value identifying the exception event is written to bits 11–0 of the EXPEVT
register.
Instruction execution jumps to the vector location designated by either the sum of the vector
base address and offset H'00000400 in the vector table in a TLB miss trap, or by the sum of the
vector base address and offset H'00000100 for exceptions other than TLB miss traps, to invoke
the exception handler.
Power-On Reset
Manual Reset
Conditions: BREQ pin high and RESET low
Operations: EXPEVT set to H'000, VBR and SR initialized, branch to PC = H'A0000000.
Conditions: BREQ pin low and RESET low
Operations: EXPEVT set to H'020, VBR and SR initialized, branch to PC = H'A0000000.
Initialization sets the VBR register to H'0000000. In SR, the MD, RB and BL bits are set to
1 and the IMASK field is set to B'1111. The CPU and on-chip supporting modules are
initialized. See the register descriptions in the relevant sections for details. A power-on
reset must always be performed when powering on.
Initialization sets the VBR register to H'0000000. In SR, the MD, RB, and BL bits are set
to 1 and the IMASK field is set to B'1111. The CPU and on-chip supporting modules are
initialized. See the register descriptions in the relevant sections for details.
Individual Exception Operations
Resets
Types of Reset
BREQ
High
Low
Conditions for Transition
to Reset State
RESET
Low
Low
CPU
Initialized
Initialized
On-Chip Supporting Modules
(See register configuration in
relevant sections)
Internal State
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