HD6417708SF60V Renesas Electronics America, HD6417708SF60V Datasheet - Page 235
HD6417708SF60V
Manufacturer Part Number
HD6417708SF60V
Description
IC SUPERH MPU ROMLESS 208LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417708SF60V.pdf
(635 pages)
Specifications of HD6417708SF60V
Core Processor
SH-2
Core Size
32-Bit
Speed
60MHz
Connectivity
EBI/EMI, SCI, SmartCard
Peripherals
POR, WDT
Number Of I /o
8
Program Memory Type
ROMless
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
208-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Ram Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417708SF60V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD6417708SF60V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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Bits 9 and 8—CAS-Before-RAS Refresh RAS Assert Time (TRAS1, TRAS0): These bits set the
RAS assert period for CAS-before-RAS refreshing of the DRAM connected to area 2.
In the SH7708, set the same values in the TRAS bits in MCR and DCR.
Bit 9: TRAS1
0
1
Bit 6—Burst Enable (BE): Specifies whether to conduct a burst access of the DRAM connected to
area 2.
Bit 6: BE
0
1
Bits 4 and 3—Address Multiplex (AMX1, AMX0): These bits specify address multiplexing for
the DRAM connected to area 2.
Bit 4: AMX1
0
1
Bit 2—Refresh Control (RFSH): Determines whether or not refreshing of the DRAM connected to
area 2 is performed.
Bit 2: RFSH
0
1
Bit 8: TRAS0
0
1
0
1
Bit 3: AMX0
0
1
0
1
Description
Burst disabled
High-speed page mode access
Description
No refresh
Refresh
Description
2 cycles
3 cycles
4 cycles
5 cycles
Description
8-bit column address product
9-bit column address product
10-bit column address product
11-bit column address product
(Initial value)
(Initial value)
(Initial value)
(Initial value)
215
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