HD64F38024DV Renesas Electronics America, HD64F38024DV Datasheet - Page 817
HD64F38024DV
Manufacturer Part Number
HD64F38024DV
Description
IC H8/SLP MCU FLASH 80QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300L SLPr
Datasheets
1.US38024-BAG1.pdf
(684 pages)
2.DF36012GFYV.pdf
(1021 pages)
3.DF38102HV.pdf
(145 pages)
Specifications of HD64F38024DV
Core Processor
H8/300L
Core Size
8-Bit
Speed
10MHz
Connectivity
SCI
Peripherals
LCD, PWM, WDT
Number Of I /o
51
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number:
HD64F38024DV
Manufacturer:
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The operands are interpreted as follows:
The following branch sizes can be specified.
Refer to section 11.3, .DISPSIZE FBR, section 3.2.2, br_relative, and section
3.2.2, [no]optimize, for the setting used when the branch size specifier is
omitted.
(1) <loop counter>=<initial value>
(2) <end value>
(3) <increment value>
Operation
8
16
The increment value is the amount the loop counter is incremented or
decremented on each loop iteration.
The increment direction is specified by a plus (+) to indicate a positive
increment direction and a minus (–) to indicate a negative decrement
direction.
Plus (+) is taken as the default when no increment direction is specified.
The increment value must have an addressing mode that can be specified as
the source operand for the ADD and SUB instructions.
The value +#1 is used as the default when no increment value is specified.
This specifies the loop counter’s initial value.
The loop counter must be a register.
The initial value must have an addressing mode that can be specified as the
source operand of the MOV instruction.
The end value is the value which is compared with the loop counter.
There are two types of iteration conditions as follows:
The end value must have an addressing mode that can be specified as the
source operand of the CMP instruction.
Positive increment direction: <loop counter>
Negative increment direction: <loop counter>
Branch Size
8 bits
16 bits
<end value>
<end value>
803
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