HD64F38024DV Renesas Electronics America, HD64F38024DV Datasheet - Page 318
HD64F38024DV
Manufacturer Part Number
HD64F38024DV
Description
IC H8/SLP MCU FLASH 80QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300L SLPr
Datasheets
1.US38024-BAG1.pdf
(684 pages)
2.DF36012GFYV.pdf
(1021 pages)
3.DF38102HV.pdf
(145 pages)
Specifications of HD64F38024DV
Core Processor
H8/300L
Core Size
8-Bit
Speed
10MHz
Connectivity
SCI
Peripherals
LCD, PWM, WDT
Number Of I /o
51
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Quantity
Price
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Part Number:
HD64F38024DV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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(2) float type
304
The float type is internally represented by a 1-bit sign, an 8-bit exponent, and a 23-bit
mantissa.
i. Normalized numbers
ii. Denormalized numbers
The sign indicates the sign of the value, either 0 (positive) or 1 (negative). The exponent is
between 1 and 254 (2
value. The range is between 126 and 127. The mantissa is between 0 and 2
actual mantissa is interpreted as the value of which the 2
by the decimal point. Values of normalized numbers are as follows:
( 1)
Example:
31 30
Sign:
Exponent: 10000000
Mantissa: 1.11
Value:
The sign indicates the sign of the value, either 0 (positive) or 1 (negative). The exponent is
0 and the actual exponent is 126. The mantissa is between 1 and 2
mantissa is interpreted as the value of which the 2
decimal point. Values of denormalized numbers are as follows:
( 1)
Example:
31 30
Sign:
Exponent:
Mantissa: 0.11
Value:
1 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
sign
sign
2
2
exponent 127
126
+
0.75
1.75
126
23 22
23 22
((mantissa)
(2)
(2)
= 1.75
= 0.75, where
2
(1+(mantissa)
2
126
8
1
(2)
2). The actual exponent is gained by subtracting 127 from this
=
127 = 1, where
3.5
2
23
)
(2)
indicates binary
2
23
)
(2)
indicates binary
23
rd bit is 0 and this bit is followed by the
23
rd bit is 1 and this bit is followed
0
0
23
1, and the actual
23
1. The
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