HD64F38024DV Renesas Electronics America, HD64F38024DV Datasheet - Page 130
HD64F38024DV
Manufacturer Part Number
HD64F38024DV
Description
IC H8/SLP MCU FLASH 80QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300L SLPr
Datasheets
1.US38024-BAG1.pdf
(684 pages)
2.DF36012GFYV.pdf
(1021 pages)
3.DF38102HV.pdf
(145 pages)
Specifications of HD64F38024DV
Core Processor
H8/300L
Core Size
8-Bit
Speed
10MHz
Connectivity
SCI
Peripherals
LCD, PWM, WDT
Number Of I /o
51
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Part Number:
HD64F38024DV
Manufacturer:
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Notes: 1. * indicates an empty area generated by boundary alignment.
116
When this option is not specified, linkage is based on the boundary alignment of sections after
compilation.
Specifying this option fills the unnecessary empty areas generated by boundary alignment,
reducing the size of the data sections as a whole.
Example
<tp1.c>
long a;
char b,c;
Sizes of data sections after compilation (taking the output of the SH compiler as an example):
tp1.obj : 4 + 1 + 1 = 6 bytes
tp2.obj : 1 + 3 [*] + 4 + 1 = 9 bytes
Sizes of data sections for tp1.obj and tp2.obj after linkage:
Remarks
The function of this option is not applicable to object files generated by the assembler.
Specification of this option is invalid in any of the following cases:
Optimization will not be applied in the linkage of a relocatable file that was generated with this
option specified.
2. The sizes of the data sections after compilation may differ from those in the above
example according to the specification of other options, etc. at compilation.
When data_stuff is not specified
When data_stuff is specified
form=library or object is specified
An absolute load module is input
memory=low is specified
nooptimize is not specified
Object files are linked based on the boundary alignment of the sections (conventional
process).
6 bytes [tp1] + 2 bytes [*] + 9 bytes [tp2] = 17 bytes
Linkage is performed with filling of the unnecessary empty spaces generated
between sections by boundary alignment.
(4 + 1 + 1) bytes + 1 byte + 1 byte [*] + 4 bytes + 1 byte = 13 bytes
long e;
char f;
<tp2.c>
char d;
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