HD64F38024DV Renesas Electronics America, HD64F38024DV Datasheet - Page 378

• Manufacturer Part Number: HD64F38024DV
• Description: IC H8/SLP MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300L SLPr

Specifications of HD64F38024DV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SCI
• Peripherals: LCD, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Table 10.28 Intrinsic Functions (cont)
Item
Condition
code
operation
Condition
code
operation
364
Specification
int ovfaddc(char dst,char src,char *rst)
int ovfadduc(unsigned char dst,
unsigned char src,unsigned char *rst)
int ovfaddw(int dst,int src,int *rst)
int ovfadduw(unsigned int dst,
unsigned int src,unsigned int *rst)
int ovfaddl(long dst,long src,long *rst)
int ovfaddul(unsigned long dst,
unsigned long src,unsigned long *rst)
int ovfsubc(char dst,char src,char *rst)
int ovfsubuc(unsigned char dst, unsigned
char src,unsigned char *rst)
int ovfsubw(int dst,int src,int *rst)
int ovfsubuw(unsigned int dst,
unsigned int src,unsigned int *rst)
int ovfsubl(long dst,long src,long *rst)
int ovfsubul(unsigned long dst,
unsigned long src,unsigned long *rst)
int ovfshalc(char des,char *rst)
int ovfshalw(int dst,int *rst)
int ovfshall(long dst,long *rst)
Int ovfshlluc(unsigned char des,
unsigned char *rst)
int ovfshlluw(unsigned int dst,
unsigned int *rst)
int ovfshllul(unsigned long dst,
unsigned long *rst)
int ovfnegc(char dst,char *rst)
int ovfnegw(int dst,int *rst)
int ovfnegl(long dst,long *rst)
Function
Sets the results of dst + src in *rst
and reflects the results in the
condition code register
Set the results of dst – src in *rst and
reflects the results in the condition
code register
Sets the results of dst << 1 in *rst and
reflects the results in the condition
code register (arithmetical shift)
Sets the results of dst << 1 in *rst and
reflects the results in the condition
code register (logical shift)
Sets the 2's complement of dst in *rst
and reflects the results in the
condition code register