DEMO9S08EL32 Freescale Semiconductor, DEMO9S08EL32 Datasheet - Page 252

• Manufacturer Part Number: DEMO9S08EL32
• Description: BOARD DEMO FOR 9S08 EL MCU
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of DEMO9S08EL32

• Contents: Evaluation Board
• Processor To Be Evaluated: MC9S08EL32
• Data Bus Width: 8 bit
• Interface Type: RS-232, USB
• Operating Supply Voltage: 12 V
• Silicon Manufacturer: Freescale
• Core Architecture: HCS08
• Core Sub-architecture: HCS08
• Silicon Core Number: MC9S08
• Silicon Family Name: S08EL
• Rohs Compliant: Yes
• For Use With/related Products: MC9S08EL32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Serial Communications Interface (S08SCIV4)
14.2
The SCI has eight 8-bit registers to control baud rate, select SCI options, report SCI status, and for
transmit/receive data.
Refer to the direct-page register summary in the
assignments for all SCI registers. This section refers to registers and control bits only by their names. A
Freescale-provided equate or header file is used to translate these names into the appropriate absolute
addresses.
14.2.1
This pair of registers controls the prescale divisor for SCI baud rate generation. To update the 13-bit baud
rate setting [SBR12:SBR0], first write to SCIxBDH to buffer the high half of the new value and then write
to SCIxBDL. The working value in SCIxBDH does not change until SCIxBDL is written.
SCIxBDL is reset to a non-zero value, so after reset the baud rate generator remains disabled until the first
time the receiver or transmitter is enabled (RE or TE bits in SCIxC2 are written to 1).
254
RXEDGIE
SBR[12:8]
Reset
LBKDIE
Field
4:0
7
6
W
R
Register Definition
LBKDIE
SCI Baud Rate Registers (SCIxBDH, SCIxBDL)
LIN Break Detect Interrupt Enable (for LBKDIF)
0 Hardware interrupts from LBKDIF disabled (use polling).
1 Hardware interrupt requested when LBKDIF flag is 1.
RxD Input Active Edge Interrupt Enable (for RXEDGIF)
0 Hardware interrupts from RXEDGIF disabled (use polling).
1 Hardware interrupt requested when RXEDGIF flag is 1.
Baud Rate Modulo Divisor — The 13 bits in SBR[12:0] are referred to collectively as BR, and they set the
modulo divide rate for the SCI baud rate generator. When BR = 0, the SCI baud rate generator is disabled to
reduce supply current. When BR = 1 to 8191, the SCI baud rate = BUSCLK/(16×BR). See also BR bits in
Table
0
7
14-2.
= Unimplemented or Reserved
RXEDGIE
MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3
0
6
Figure 14-4. SCI Baud Rate Register (SCIxBDH)
Table 14-1. SCIxBDH Field Descriptions
0
0
5
Memory
SBR12
0
4
Description
chapter of this data sheet for the absolute address
SBR11
3
0
SBR10
0
2
Freescale Semiconductor
SBR9
0
1
SBR8
0
0