DEMO9S08EL32 Freescale Semiconductor, DEMO9S08EL32 Datasheet - Page 225

• Manufacturer Part Number: DEMO9S08EL32
• Description: BOARD DEMO FOR 9S08 EL MCU
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of DEMO9S08EL32

• Contents: Evaluation Board
• Processor To Be Evaluated: MC9S08EL32
• Data Bus Width: 8 bit
• Interface Type: RS-232, USB
• Operating Supply Voltage: 12 V
• Silicon Manufacturer: Freescale
• Core Architecture: HCS08
• Core Sub-architecture: HCS08
• Silicon Core Number: MC9S08
• Silicon Family Name: S08EL
• Rohs Compliant: Yes
• For Use With/related Products: MC9S08EL32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The error also comes into effect with transmitted bit times. Using the previous example with a SLCBT
value of 34, transmitted bits will appear as 34 SLIC clock periods long. This is one SLIC clock short of
the proper length. Depending on the frequency of the SLIC clock, one period of the SLIC clock might be
a large or a small fraction of one ideal bit time. Raising the frequency of the SLIC clock will reduce this
error relative to the ideal bit time, improving the resolution of the SLIC clock relative to the bit rate of the
bus. In any case, the error is still one SLIC clock cycle. Raising the SLIC clock frequency, however,
requires programming a higher value for SLCBT to maintain the same target bit rate.
Smaller values of SLCBT combined with higher values of the SLIC clock frequency (smaller clock period)
will give faster bit rates, but the SLIC clock period becomes an increasingly significant portion of one bit
time.
Because BTM mode does not perform any synchronization and relies on the accuracy of the data provided
by the user software to set its sample point and generate transmitted bits, the constraint on maximum
speeds is only limited to the limits imposed by the digital filter delay and the SLIC input clock. Because
the digital filter delay cannot be less than 16 SLIC clock cycles, the fastest possible pulse which would
pass the filter is 16 clock periods at 8 MHz, or 500,000 bits/second. The values shown in
the same values shown in
minimum digital filter settings (prescaler = divide by 1) under perfect conditions.
Freescale Semiconductor
This example assumes a SLCBT value of 30 (0x1E).
Transmitted bits will be sent out as 30 SLIC clock cycles long.
The proper closest SLCBT setting would be 34 (0x22),
which gives the ideal sample point of 17 SLIC clocks and
transmitted bits are 34 SLIC clocks long.
FILTER CLOCK
(³1 PRESCALE)
(³1 PRESCALE)
UNFILTERED
SLIC CLOCK
FILTERED
RX DATA
RX DATA
COUNTING DOWN
FILTER BEGINS
MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3
Figure 12-21. BTM Mode Receive Byte Sampling Example
16 FILTER CLOCKS
(³1 PRESCALE)
Table 12-15
AND TOGGLES FILTER OUTPUT
FILTER REACHES 0X0
and indicate the absolute fastest bit rates which could just pass the
(1/2 OF SLCBT VALUE)
15 SLIC CLOCKS
(BASED ON SLCBT VALUE)
SLIC SAMPLE POINT
FILTER BEGINS
COUNTING UP
(ACTUAL FILTERED BIT LENGTH)
IDEAL SLIC SAMPLE POINT (17 SLIC CLOCKS)
35 SLIC CLOCKS
16 FILTER CLOCKS
(³1 PRESCALE)
AND TOGGLES FILTER OUTPUT
FILTER REACHES 0XF
Table 12-14
are
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