MT48H8M32LFB5-10 Micron Technology Inc, MT48H8M32LFB5-10 Datasheet - Page 45

• Manufacturer Part Number: MT48H8M32LFB5-10
• Description: IC SDRAM 256MBIT 100MHZ 90VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT48H8M32LFB5-10

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 256M (8Mx32)
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 90-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PDF: 09005aef80d460f2/Source: 09005aef80cd8d41
256Mb SDRAM x32_2.fm - Rev. G 6/05
10. For a READ without auto precharge interrupted by a READ (with or without auto pre-
11. For a READ without auto precharge interrupted by a WRITE (with or without auto pre-
12. For a WRITE without auto precharge interrupted by a READ (with or without auto pre-
13. For a WRITE without auto precharge interrupted by a WRITE (with or without auto pre-
14. For a READ with auto precharge interrupted by a READ (with or without auto precharge),
15. For a READ with auto precharge interrupted by a WRITE (with or without auto precharge),
16. For a WRITE with auto precharge interrupted by a READ (with or without auto precharge),
17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto pre-
7. READs or WRITEs to bank m listed in the Command (Action) column include READs or
8. CONCURRENT AUTO PRECHARGE: Bank n will initiate the auto precharge command when
9. Burst in bank n continues as initiated.
WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled.
its burst has been interrupted by bank m burst.
charge), the READ to bank m will interrupt the READ on bank n, CAS latency later (Figure
10 consecutive read bursts).
charge), the WRITE to bank m will interrupt the READ on bank n when registered (Figures
12 and 13). DQM should be used one clock prior to the WRITE command to prevent bus
contention.
charge), the READ to bank m will interrupt the WRITE on bank n when registered (Figure
20), with the data-out appearing CAS latency later. The last valid WRITE to bank n will be
data-in registered one clock prior to the READ to bank m.
charge), the WRITE to bank will interrupt the WRITE on bank n when registered (Figure
18). The last valid WRITE to bank n will be data-in registered one clock prior to the READ
to bank m.
the READ to bank m will interrupt the READ on bank n, CAS latency later. The PRECHARGE
to bank n will begin when the READ to bank m is registered.
the WRITE to bank m will interrupt the READ on bank n when registered. DQM should be
used two clocks prior to the WRITE command to prevent bus contention. The PRECHARGE
to bank n will begin when the WRITE to bank m is registered.
the READ to bank m will interrupt the WRITE on bank n when registered, with the data-
out appearing CAS latency later. The PRECHARGE to bank n will begin after
where
be data-in registered one clock prior to the READ to bank m.
charge), the WRITE to bank m interrupt the WRITE on bank n when registered. The PRE-
CHARGE to bank n will begin after
m is registered. The last valid WRITE to bank n will be data registered one clock to the
WRITE to bank m.
t
WR begins when the READ to bank m is registered. The last valid WRITE bank n will
45
t
WR is met, where
Micron Technology, Inc., reserves the right to change products or specifications without notice.
256Mb: x32 Mobile SDRAM
t
WR begins when the WRITE to bank
©2003 Micron Technology, Inc. All rights reserved.
Truth Tables
t
WR is met,