MT48H8M32LFB5-10 Micron Technology Inc, MT48H8M32LFB5-10 Datasheet - Page 31

• Manufacturer Part Number: MT48H8M32LFB5-10
• Description: IC SDRAM 256MBIT 100MHZ 90VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT48H8M32LFB5-10

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 256M (8Mx32)
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 90-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

WRITEs
Figure 16: WRITE Command
PDF: 09005aef80d460f2/Source: 09005aef80cd8d41
256Mb SDRAM x32_2.fm - Rev. G 6/05
WRITE bursts are initiated with a WRITE command, as shown in Figure 15 on page 30.
The starting column and bank addresses are provided with the WRITE command, and
auto precharge is either enabled or disabled for that access. If auto precharge is enabled,
the row being accessed is precharged at the completion of the burst. For the generic
WRITE commands used in the following illustrations, auto precharge is disabled.
During WRITE bursts, the first valid data-in element will be registered coincident with
the WRITE command. Subsequent data elements will be registered on each successive
positive clock edge. Upon completion of a fixed-length burst, assuming no other com-
mands have been initiated, the DQs will remain High-Z and any additional input data
will be ignored (see Figure 17). A full-page burst will continue until terminated. (At the
end of the page, it will wrap to column 0 and continue.)
Data for any WRITE burst may be truncated with a subsequent WRITE command, and
data for a fixed-length WRITE burst may be immediately followed by data for a WRITE
command. The new WRITE command can be issued on any clock following the previous
WRITE command, and the data provided coincident with the new command applies to
the new command. An example is shown in Figure 17 on page 32. Data n + 1 is either the
last of a burst of two or the last desired of a longer burst. The 256Mb SDRAM uses a pipe-
lined architecture and therefore does not require the 2n rule associated with a prefetch
architecture. A WRITE command can be initiated on any clock cycle following a previous
A9, A11
A0–A8
BA0, 1
RAS#
CAS#
WE#
CKE
A10
CLK
CS#
31
HIGH
VALID ADDRESS
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DISABLE AUTO PRECHARGE
ENABLE AUTO PRECHARGE
ADDRESS
COLUMN
ADDRESS
BANK
256Mb: x32 Mobile SDRAM
DON’T CARE
©2003 Micron Technology, Inc. All rights reserved.
Operation