MT48H8M32LFB5-10 Micron Technology Inc, MT48H8M32LFB5-10 Datasheet
MT48H8M32LFB5-10
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MT48H8M32LFB5-10 Summary of contents
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Mobile SDRAM MT48LC8M32LF, MT48V8M32LF, MT48H8M32LF - 2 Meg banks For the latest data sheet, refer to Micron’s Web site: Features • Low voltage power supply • Partial array self refresh power-saving mode • Temperature Compensated Self ...
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Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 1: Functional Block Diagram 8 Meg x 32 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Tables Table 1: Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... MT48H8M32LFF5-8 MT48H8M32LFF5-10 MT48H8M32LFB5-75 MT48H8M32LFB5-8 MT48H8M32LFB5-10 FBGA Part Number System Due to space limitations, FBGA-packaged components have an abbreviated part mark- ing that is different from the part number. For a quick conversion of an FBGA code, see the FBGA part marking decoder on Micron’s Web site, www.micron.com/decoder. ...
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... The 256Mb SDRAM is designed to operate in 3.3V, 2.5V, and 1.8V low-power memory systems. An auto refresh mode is provided, along with a power-saving, deep power- down mode. All inputs and outputs are LVTTL-compatible. ...
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Ball Assignment Figure 2: 90-Ball VFBGA (Top View) PDF: 09005aef80d460f2/Source: 09005aef80cd8d41 256Mb SDRAM x32_2.fm - Rev DQ26 DQ24 DQ28 DQ27 ...
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... A0–A11) and READ/WRITE command (column-address A0–A8; with A10 defining auto precharge) to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine if all banks are to be precharged (A10 HIGH) or bank selected by BA0, BA1. The address inputs also provide the op-code during a LOAD MODE REGISTER command ...
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Functional Description In general, the 256Mb SDRAMs (2 Meg banks) are quad-bank DRAMs that oper- ate at 3.3V, 2.5V, and 1.8V and include a synchronous interface (all signals are registered on the positive edge of the ...
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Burst Length Read and write accesses to the SDRAM are burst oriented, with the burst length being programmable, as shown in Figure 3. The burst length determines the maximum num- ber of column locations that can be accessed for a ...
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Figure 3: Mode Register Definition BA1 M13 13 0 *Should program M10 = “0, 0” to ensure compatibility with future devices. PDF: 09005aef80d460f2/Source: 09005aef80cd8d41 256Mb SDRAM x32_2.fm - Rev. G 6/05 BA0 A11 A10 ...
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Table 5: Burst Definition Table Burst Length Full Page (y) Notes: 1. For full-page accesses 512. 2. For block. 3. For the block. 4. For the ...
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DQs will start driving after T1 and the data will be valid by T2, as shown in Figure 4. Table 5 indicates the operating frequencies at which each CAS latency setting ...
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Figure 4: CAS Latency Table 6: CAS Latency PDF: 09005aef80d460f2/Source: 09005aef80cd8d41 256Mb SDRAM x32_2.fm - Rev CLK COMMAND READ NOP CLK COMMAND READ NOP t ...
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Figure 5: Low Power Extended Mode Register Table Notes: 1. E13 and E12 (BA1 and BA0) must be “1, 0” to select the extended mode register (vs. the base mode register). 2. Default EMR values are full array for PASR, ...
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... Partial Array Self Refresh For further power savings during self refresh, the partial array self refresh (PASR) feature allows the controller to select the amount of memory that will be refreshed during self refresh. The refresh options are all banks (banks and 3), two banks (banks 0 and 1), and one bank (bank 0) ...
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Commands Table 7 provides a quick reference of available commands. This is followed by a written description of each command. Three additional Truth Tables appear following "Opera- tion" on page 21; these tables provide current state/next state information. Table 7: ...
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... Input data appearing on the DQs is written to the memory array subject to the DQM input logic level appearing coincident with the data given DQM signal is registered LOW, the corresponding data will be written to mem- ory ...
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READ or WRITE burst, except in the full-page burst mode, where auto precharge does not apply. Auto precharge is non persistent in that it is either enabled or disabled for each individual ...
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... DEEP POWER-DOWN DEEP POWER-DOWN is an operating mode to achieve maximum power reduction by eliminating the power of the whole memory array of the devices. Array data will not be retained once the device enters deep power-down mode. The settings in the mode and extended mode register will be retained during deep power-down. ...
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Operation Bank/Row Activation Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row in that bank must be “opened.” This is accomplished via the ACTIVE command, which selects both the bank and the ...
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Figure 7: Example: Meeting READs READ bursts are initiated with a READ command, as shown in Figure 8. The starting column and bank addresses are provided with the READ command, and auto precharge is either enabled or disabled for that ...
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Figure 8: READ Command Upon completion of a burst, assuming no other commands have been initiated, the DQs will go High-Z. A full-page burst will continue until terminated. (At the end of the page, it will wrap to column 0 ...
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Figure 9: CAS Latency This is shown in Figure 10 for CAS latencies of one, two, and three; data element either the last of a burst of four or the last desired of a longer burst. ...
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Figure 10: Consecutive READ Bursts COMMAND ADDRESS COMMAND ADDRESS COMMAND ADDRESS Note: Each READ command may be to either bank. DQM is LOW. PDF: 09005aef80d460f2/Source: 09005aef80cd8d41 256Mb SDRAM x32_2.fm - Rev CLK READ NOP NOP ...
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Figure 11: Random READ Accesses Note: Each READ command may be to either bank. DQM is LOW. Data from any READ burst may be truncated with a subsequent WRITE command, and data from a fixed-length READ burst may be immediately ...
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READ burst, provided that I/O contention can be avoided given system design, there may be a possibility that the device driving the ...
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Figure 12: READ to WRITE Note The READ command may be to any bank, and the WRITE command may be to any bank burst of one is used, then DQM is not required. Figure 13: ...
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Figure 14: READ to PRECHARGE Note: DQM is LOW. Full-page READ bursts can be truncated with the BURST TERMINATE command, and fixed-length READ bursts may be truncated with a BURST TERMINATE command, pro- vided that auto precharge was not activated. ...
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Figure 15: Terminating a READ Burst COMMAND ADDRESS COMMAND ADDRESS COMMAND ADDRESS Note: DQM is LOW. PDF: 09005aef80d460f2/Source: 09005aef80cd8d41 256Mb SDRAM x32_2.fm - Rev CLK READ NOP NOP BANK, COL OUT OUT ...
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WRITEs WRITE bursts are initiated with a WRITE command, as shown in Figure 15 on page 30. The starting column and bank addresses are provided with the WRITE command, and auto precharge is either enabled or disabled for that access. ...
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WRITE command. Full-speed random write accesses within a page can be performed to the same bank, as shown in Figure 19, or each subsequent WRITE may be performed to a different bank. Figure 17: WRITE Burst Note ...
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In addition, when truncating a WRITE burst, the DQM signal must be used to mask input data for the clock edge prior to, and the clock edge coincident with, the PRE- CHARGE command. An example is shown in Figure 21. ...
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Figure 21: WRITE to PRECHARGE Note: DQM could remain LOW in this example if the WRITE burst is a fixed length of two. Fixed-length or full-page WRITE bursts can be truncated with the BURST TERMINATE command. When truncating a WRITE ...
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... DEEP POWER-DOWN Deep power-down mode is a maximum power savings feature achieved by shutting off the power to the entire memory array of the device. Data on the memory array will not be retained once deep power-down mode is executed. Deep power-down mode is entered by having all banks idle then CS# and WE# held LOW with RAS# and CAS# HIGH at the rising edge of the clock, while CKE is LOW ...
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Figure 23: PRECHARGE Command Figure 24: Power-Down CLK CKE COMMAND In order to exit deep power-down mode, CKE must be asserted high. After exiting, the following sequence is needed in order to enter a new command: 1. Maintain NOP input ...
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CLOCK SUSPEND The clock suspend mode occurs when a column access/burst is in progress and CKE is registered LOW. In the clock suspend mode, the internal clock is deactivated, “freezing” the synchronous logic. For each positive clock edge on which ...
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Figure 25: Clock Suspend During WRITE Burst Note: For this example greater, and DM is LOW. Figure 26: Clock Suspend During READ Burst Note: For this example greater, and ...
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Figure 27: READ With Auto Precharge Interrupted by a READ COMMAND Internal States ADDRESS Note: DQM is LOW. Figure 28: READ With Auto Precharge Interrupted by a WRITE COMMAND Internal States ADDRESS Note: DQM is HIGH prevent ...
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WRITE with Auto Precharge 3. Interrupted by a READ (with or without auto precharge): A READ to bank m will inter- rupt a WRITE on bank n when registered, with the data-out appearing CAS latency later. The precharge to bank ...
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Truth Tables Table 8: Truth Table – CKE Notes: 1–4 CKE CKE Current State n Power-Down Self Refresh Clock Suspend Deep Power-Down L H Power-Down Deep Power-Down Self Refresh Clock Suspend H L All Banks Idle All ...
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Table 9: Truth Table – Current State Bank n, Command To Bank n Notes: 1–6; notes appear below table Current State CS# RAS# CAS# WE# COMMAND (ACTION) Any Idle ...
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The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must be applied on each positive clock edge during these states. Refreshing: Starts with registration of an AUTO REFRESH command and ends when ...
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Table 10: Truth Table – Current State Bank n, Command To Bank m Notes: 1–6; notes appear below and on next page Current State CS# RAS# CAS# Any Idle X X Row L L Activating, L ...
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READs or WRITEs to bank m listed in the Command (Action) column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled. 8. CONCURRENT AUTO PRECHARGE: Bank n will initiate the auto precharge ...
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Electrical Specifications Absolute Maximum Ratings Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other condi- tions above those indicated in ...
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Table 13: DC Electrical Characteristics and Operating Conditions (V version) Notes notes appear on page 54; V Parameter/Condition Supply Voltage I/O Supply Voltage Input High Voltage: Logic 1; All inputs Input Low Voltage: Logic 0; All inputs ...
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Table 15: Electrical Characteristics and Recommended AC Operating Conditions Notes 11; notes appear on page 54 AC Characteristics Parameter Access time from CLK (pos. edge) Address hold time Address setup time CLK high-level width CLK low-level ...
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Table 16: AC Functional Characteristics Notes 11; notes appear on page 54 Parameter READ/WRITE command to READ/WRITE command CKE to clock disable or power-down entry mode CKE to clock enable or power-down exit setup mode ...
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Table 18: I Specifications and Conditions (V version) DD Notes 11, 13; notes appear on page 54; V Parameter/Condition Operating current: active mode; Burst = 2; READ WRITE (MIN) Standby current: ...
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Table 20 – Self Refresh Current Options DD Notes: 4, 30; notes appear on page 54 and page 55 Temperature Compensated Self Refresh Parameter/Condition Self Refresh Current: CKE = LOW – 4-bank refresh Self Refresh Current: CKE = ...
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Figure 32: Typical Self Refresh Current vs. Temperature – 2.5V Part 600 550 500 450 400 350 300 250 200 150 100 50 0 -40 -30 -20 -10 Figure 33: Typical Self Refresh Current vs. Temperature – 1.8V Part 450 ...
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Table 21: Capacitance Note: 2; notes appear on page 54 Parameter Input Capacitance: CLK Input Capacitance: All other input-only balls Input/Output Capacitance: DQs PDF: 09005aef80d460f2/Source: 09005aef80cd8d41 256Mb SDRAM x32_2.fm - Rev. G 6/05 256Mb: x32 Mobile SDRAM Symbol MIN MAX ...
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Notes 1. All voltages referenced This parameter is sampled. V biased at 0.9V, 1.25V, and 1.4V respectively MHz with minimum cycle time and the outputs open. 4. Enables on-chip refresh and ...
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CLK must be toggled a minimum of two times during this period. 21. Based on 22 cannot be greater than one third of the cycle rate pulse width ≤ 3ns. 23. The clock frequency must ...
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Timing Diagrams Figure 34: Initialize and Load Mode Register CLK ( ( ) ) t t CKS CKH ( ( ) ) CKE ( ( ) ) t t CMS CMH ( ( ) ) ...
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Figure 35: Power-Down Mode CLK CKE t CKS t CKH t CMS t CMH COMMAND PRECHARGE DQML, DQMU A0-A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK(S) High-Z DQ Two clock cycles ...
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Figure 36: Clock Suspend Mode CLK t CKS t CKH CKE t CKS t CKH t CMS t CMH COMMAND READ NOP t CMS t CMH DQM 0 A0-A9, ...
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Figure 37: Auto Refresh Mode T0 CLK t CK CKE t CKS t CKH t CMS t CMH COMMAND PRECHARGE DQM 0-3 A0-A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK(S) High-Z DQ Precharge all ...
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Figure 38: Self Refresh Mode T0 CLK t CK CKE t CKS t CKH t CMS t CMH COMMAND PRECHARGE DQM 0-3 A0-A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK(S) High ...
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Figure 39: READ – Without Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS DQM 0 ROW A0–A9, A11 ...
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Figure 40: Read – With Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS DQM 0 ROW A0–A9, A11 ...
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Figure 41: Single Read – Without Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS DQM 0 ROW A0–A9, A11 t AS ...
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Figure 42: Single Read – With Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM 0 ROW A0–A9, A11 ROW A10 ...
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Figure 43: Alternating Bank Read Accesses CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS DQM 0 ROW A0–A9, A11 ENABLE AUTO ...
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Figure 44: Read – Full-page Burst CLK CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS DQM 0 A0-A9, A11 COLUMN m ...
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Figure 45: Read – DQM Operation CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS DQM 0 ROW A0–A9, A11 ...
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Figure 46: Write – Without Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS DQM 0 A0–A9, A11 COLUMN m 3 ROW ...
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Figure 47: Write – With Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS DQM 0 A0–A9, A11 COLUMN m 2 ROW ...
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Figure 48: Single Write – Without Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS DQM 0 ROW A0–A9, A11 t AS ...
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Figure 49: Single Write – With Auto Precharge CLK t CKS t CKH CKE t CMS t CMH NOP 3 COMMAND ACTIVE DQM 0 ROW A0–A9, A11 ...
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Figure 50: Alternating Bank Write Accesses CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP WRITE t CMS DQM 0 COLUMN m 2 ROW A0–A9, ...
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Figure 51: Write – Full-page Burst CLK CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM 0 A0-A9, A11 ROW ROW A10 ...
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Figure 52: Write – DQM Operation CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM 0 A0–A9, A11 ROW ROW A10 t AS ...
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Package Dimensions Figure 53: 90-Ball VFBGA (8mm x 13mm) 0.65 ±0.05 SEATING PLANE C 0.10 C 90X Ø0.45 ±0.05 SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. THE PRE- REFLOW DIAMETER IS Ø0.42 BALL A9 11.20 ±0.10 5.60 ±0.05 3.20 ...